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2012-10-07target-sparc: Move taddcctv and tsubcctv out of lineRichard Henderson1-102/+6
The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy TccRichard Henderson1-38/+53
Share more code between unconditional and conditional paths. Move the computation of the trap number into the conditional BB; avoid using temporaries that have gone out of scope (cpu_tmp32) or rely on local temps (cpu_dst). Fully fold the exception number when the trap number is %g0+imm. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Move sdivx and udivx out of lineRichard Henderson1-50/+2
The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use movcond in gen_generic_branchRichard Henderson1-11/+7
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare and movcond in MOVRRichard Henderson1-17/+14
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare and movcond in MOVCCRichard Henderson1-24/+20
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare and movcond in FMOVR, FMOVCCRichard Henderson1-117/+86
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare in TccRichard Henderson1-9/+11
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Introduce DisasCompare and functions to generate itRichard Henderson1-9/+83
For the moment gen_cond et al retain their existing interface, using setcond to turn a (potential) comparison back into a boolean. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy gen_generic_branch interfaceRichard Henderson1-8/+7
The arguments passed are always the same. Pass down just DisasContext instead. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy save_npc interfaceRichard Henderson1-4/+4
Use the cpu_cond global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy gen_mov_pc_npc interfaceRichard Henderson1-6/+6
Use the cpu_cond global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy save_state interfaceRichard Henderson1-49/+49
Use the cpu_cond global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy gen_trap_ifnofpu interfaceRichard Henderson1-18/+28
We always pass cpu_cond to the cond parameter. Use that global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy flush_cond interfaceRichard Henderson1-5/+5
We always pass cpu_cond to the cond parameter. Use that global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy do_branch interfacesRichard Henderson1-20/+18
We always pass cpu_cond to the r_cond parameter. Use that global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson1-1/+2
For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-05-12Implement address masking for SPARC v9 CPUsArtyom Tarasenko1-1/+24
According to UltraSPARC - IIi User's manual: 14.1.11 Address Masking (Impdep #125) When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps transmit zero in the high-order 32-bits of the PC to their specified destination registers. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18Sparc: avoid AREG0 wrappers for memory access helpersBlue Swirl1-4/+6
Adjust generation of load and store templates so that the functions take a parameter for CPUState instead of relying on global env. Remove wrappers. Move remaining memory helpers to ldst_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-18Sparc: avoid AREG0 for memory access helpersBlue Swirl1-25/+27
Make memory access helpers take a parameter for CPUState instead of relying on global env. Introduce wrappers for load and store ops. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-14target-sparc: Don't overuse CPUStateAndreas Färber1-40/+40
Scripted conversion: sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc] sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2011-11-19Improve "ta 0" shutdownFabien Chouteau1-8/+1
This patch replace the previous implementation with this simplified and more complete version (no shutdown when psret == 1). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26target-sparc: Implement FALIGNDATA inline.Richard Henderson1-6/+26
This is a relatively simple sequence of shifts. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement BMASK/BSHUFFLE.Richard Henderson1-4/+10
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement ALIGNADDR* inline.Richard Henderson1-2/+22
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not implemeneted at all. However, this is a very simple operation so we're better off doing this inline. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement EDGE* instructions.Richard Henderson1-2/+175
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement fpack{16,32,fix}.Richard Henderson1-1/+29
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Implement PDIST.Richard Henderson1-2/+19
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Do exceptions management fully inside the helpers.Richard Henderson1-29/+0
This reduces the size of the individual translation blocks, since we only emit a single call for each FOP rather than three. In addition, clear_float_exceptions expands inline to a single byte store. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Change fpr representation to doubles.Richard Henderson1-79/+71
This allows a more efficient representation for 64-bit hosts. It should be about the same for 32-bit hosts, as we can still access the individual pieces of the double. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Undo cpu_fpr rename.Richard Henderson1-28/+28
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Extract float128 move to a function.Richard Henderson1-32/+18
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Extract common code for floating-point operations.Richard Henderson1-454/+381
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Make FPU/VIS helpers const when possible.Richard Henderson1-50/+33
This also removes the unused ENV parameter from these helpers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Pass float64 parameters instead of dt0/1 temporaries.Richard Henderson1-229/+220
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Add accessors for double-precision fpr access.Richard Henderson1-112/+130
Begin using i64 quantities to manipulate double-precision values. On a 64-bit host this will, for the moment, generate less efficient code; on a 32-bit host code quality should be largely unchanged. Code quality for 64-bit will be adjusted with a subsequent patch. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Mark fprs dirty in store accessor.Richard Henderson1-46/+8
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26target-sparc: Add accessors for single-precision fpr access.Richard Henderson1-195/+337
Load, store, and "create destination". This version attempts to change the behaviour of the translator as little as possible. We previously used cpu_tmp32 as the temporary destination, and we continue to use that. This will eventually allow a change in representation of the fprs. Change the name of the cpu_fpr array to make certain that all instances are converted. Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-26Sparc: avoid AREG0 for division op helpersBlue Swirl1-4/+8
Make [su]div{,cc} helpers take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26Sparc: avoid AREG0 for softint op helpers and Leon cache controlBlue Swirl1-3/+3
Make softint op helpers and Leon cache irq manager take a parameter for CPUState instead of relying on global env. Move the functions to int{32,64}_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-26Sparc: avoid AREG0 for CWP and PSTATE helpersBlue Swirl1-17/+17
Make CWP and PSTATE helpers take a parameter for CPUState instead of relying on global env. Remove wrapper functions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-25target-sparc: Fix order of function parametersStefan Weil1-4/+4
The MinGW-w64 gcc complains about wrong parameters for gen_helper_fpadd16_s and three other functions. gen_helper_fpadd16_s is declared like this (hidden in lots of macros): static inline void gen_helper_fpadd16s(TCGv_i32 retval, TCGv_ptr arg1, TCGv_i32 arg2, TCGv_i32 arg3); So it looks like cpu_env should be the 2nd parameter. Please review this patch as I have no environment to test it (maybe the 1st parameter should be cpu_dst?). Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23Sparc: avoid AREG0 for lazy condition code helpersBlue Swirl1-9/+9
Make lazy condition code helpers take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23Sparc: avoid AREG0 for float and VIS opsBlue Swirl1-133/+137
Make floating point and VIS ops take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-23Sparc: avoid AREG0 for raise_exception and helper_debugBlue Swirl1-13/+13
Make raise_exception() and helper_debug() take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-06Fix handling of conditional branches in delay slot of a conditional branchArtyom Tarasenko1-9/+21
Check whether dc->npc is dynamic before using its value for branch. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30SPARC64: implement %fprs dirty bitsTsuneo Saito1-0/+116
Implement %fprs.DU/DL bits. The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31 and %f32-63 respectively. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30SPARC64: fix fnor* and fnand*Tsuneo Saito1-6/+8
Fix the problem that result values are not assigned to the destination registers. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20SPARC64: add missing break on fmovdccTsuneo Saito1-0/+1
"break" is missing on V9 fmovdcc (%icc). Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20SPARC64: fix VIS1 SIMD signed compare instructionsTsuneo Saito1-16/+16
The destination registers of SIMD signed compare instructions (fcmp*<16|32>) are not FP registers but general purpose r registers. Comparisons should be freg_rs1 CMP freg_rs2, that were reversed. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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