summaryrefslogtreecommitdiff
path: root/target-sparc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2008-09-26Implement UA2005 hypervisor trapsblueswir11-2/+23
2008-09-22Add software and timer interrupt supportblueswir11-5/+29
2008-09-21Use the new concat_tl_i64 op for std and stdablueswir11-18/+6
2008-09-21Use the new concat_i32_i64 op for std and stdablueswir11-16/+20
2008-09-13Fix mulscc with high bits set in either src1 or src2blueswir11-2/+3
2008-09-11Write zeros to high bits of y, based on patch by Vince Weaverblueswir11-2/+4
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir11-35/+16
2008-09-10Partially convert float128 conversion ops to TCGblueswir11-8/+6
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir11-46/+65
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir11-76/+38
2008-09-10Convert basic float32 ops to TCGblueswir11-150/+247
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir11-8/+23
2008-09-06Fix a typo in fpsub32blueswir11-1/+1
2008-09-06Convert most env fields to TCG registersblueswir11-95/+91
2008-09-06Silence gcc warning about constant overflowblueswir11-2/+2
2008-09-02Fix sign extension problems with smul and umul (Vince Weaver)blueswir11-4/+4
2008-09-01Fix y register loads and storesblueswir11-18/+16
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir11-4/+2
2008-08-21Fix wrwim masking (Luis Pureza)blueswir11-0/+3
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir11-10/+7
2008-08-17Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir11-5/+8
2008-08-06Fix Sparc64 shiftsblueswir11-5/+3
2008-08-06Fix offset handling for ASI loads and stores (Vince Weaver)blueswir11-3/+1
2008-07-29Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir11-4/+4
2008-07-20Make UA200x features selectable, add MMU typesblueswir11-0/+6
2008-07-19Implement nucleus quad lddablueswir11-16/+12
2008-07-18Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths1-7/+6
2008-07-18wrhpr hstick_cmpr is a store, not a loadblueswir11-3/+2
2008-07-17Support for address maskingblueswir11-22/+36
2008-07-16Flushw can generate exceptions, so save PC & NPCblueswir11-0/+1
2008-07-15Really fix casblueswir11-6/+5
2008-06-29Add instruction counter.pbrook1-1/+19
2008-06-22Eliminate cpu_T[0]blueswir11-9/+9
2008-06-22Eliminate cpu_T[1]blueswir11-4/+3
2008-06-21Convert some cpu_dst uses (with loads/stores) to cpu_tmp0blueswir11-67/+67
2008-06-21Avoid brcond problems, use temps for cpu_src1 & cpu_src2blueswir11-35/+32
2008-06-15Avoid temporary variable use across basic blocks for udivxblueswir11-2/+4
2008-06-07Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir11-2/+0
2008-05-29MicroSparc I didn't have fsmuld opblueswir11-0/+1
2008-05-27Free tempsblueswir11-109/+313
2008-05-26More TCG type fixesblueswir11-11/+8
2008-05-26Fix cas on i386blueswir11-1/+1
2008-05-25remove absolete functionbellard1-5/+0
2008-05-25Nicer debug outputblueswir11-0/+2
2008-05-24More TCGv type fixes.pbrook1-1/+2
2008-05-24Fix ARM conditional branch bug.pbrook1-31/+30
2008-05-24Fix helper operand type mismatch.pbrook1-1/+2
2008-05-22Register op helpersblueswir11-0/+5
2008-05-17Generate better code for Sparc32 shiftsblueswir11-6/+21
2008-05-12Wrap long linesblueswir11-86/+175