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path: root/target-sparc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir11-4/+2
2008-08-21Fix wrwim masking (Luis Pureza)blueswir11-0/+3
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir11-10/+7
2008-08-17Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir11-5/+8
2008-08-06Fix Sparc64 shiftsblueswir11-5/+3
2008-08-06Fix offset handling for ASI loads and stores (Vince Weaver)blueswir11-3/+1
2008-07-29Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir11-4/+4
2008-07-20Make UA200x features selectable, add MMU typesblueswir11-0/+6
2008-07-19Implement nucleus quad lddablueswir11-16/+12
2008-07-18Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths1-7/+6
2008-07-18wrhpr hstick_cmpr is a store, not a loadblueswir11-3/+2
2008-07-17Support for address maskingblueswir11-22/+36
2008-07-16Flushw can generate exceptions, so save PC & NPCblueswir11-0/+1
2008-07-15Really fix casblueswir11-6/+5
2008-06-29Add instruction counter.pbrook1-1/+19
2008-06-22Eliminate cpu_T[0]blueswir11-9/+9
2008-06-22Eliminate cpu_T[1]blueswir11-4/+3
2008-06-21Convert some cpu_dst uses (with loads/stores) to cpu_tmp0blueswir11-67/+67
2008-06-21Avoid brcond problems, use temps for cpu_src1 & cpu_src2blueswir11-35/+32
2008-06-15Avoid temporary variable use across basic blocks for udivxblueswir11-2/+4
2008-06-07Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir11-2/+0
2008-05-29MicroSparc I didn't have fsmuld opblueswir11-0/+1
2008-05-27Free tempsblueswir11-109/+313
2008-05-26More TCG type fixesblueswir11-11/+8
2008-05-26Fix cas on i386blueswir11-1/+1
2008-05-25remove absolete functionbellard1-5/+0
2008-05-25Nicer debug outputblueswir11-0/+2
2008-05-24More TCGv type fixes.pbrook1-1/+2
2008-05-24Fix ARM conditional branch bug.pbrook1-31/+30
2008-05-24Fix helper operand type mismatch.pbrook1-1/+2
2008-05-22Register op helpersblueswir11-0/+5
2008-05-17Generate better code for Sparc32 shiftsblueswir11-6/+21
2008-05-12Wrap long linesblueswir11-86/+175
2008-05-11Remove someexplicit alignment checks (initial patch by Fabrice Bellard)blueswir11-44/+32
2008-05-10Add a TODO fileblueswir11-8/+0
2008-05-10suppressed fixed registersbellard1-21/+8
2008-05-10Fix compiler warningsblueswir11-3/+0
2008-05-09CPU feature selection supportblueswir11-144/+135
2008-05-07Simplify some constant loadsblueswir11-17/+14
2008-05-07Fix potential condition code problemsblueswir11-46/+58
2008-05-04Complete the TCG conversionblueswir11-36/+21
2008-05-04Avoid some brcondsblueswir11-24/+12
2008-05-03Use memory based registers in functions containing brcondsblueswir11-44/+57
2008-04-28Factorize code in translate.caurel321-0/+20
2008-04-23Document the shift valuesblueswir11-6/+6
2008-03-30Remove incorrect discards and old unused defines (blueswir1).pbrook1-64/+0
2008-03-29 Change handling of source 2blueswir11-16/+22
2008-03-29 Change handling of source register 1blueswir11-31/+36
2008-03-29 Move CPU stuff unrelated to translation to helper.cblueswir11-514/+2
2008-03-29 Rename T[012] according to their rolesblueswir11-423/+435
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