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path: root/target-xtensa/op_helper.c
AgeCommit message (Expand)AuthorFilesLines
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-4/+4
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber1-1/+3
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-4/+6
2014-03-13exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argumentAndreas Färber1-3/+6
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-2/+4
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-2/+2
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-2/+4
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber1-1/+3
2014-02-24target-xtensa: add basic checks to icache opcodesMax Filippov1-0/+5
2014-02-11exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias1-1/+2
2013-09-02target: Include softmmu_exec.h where forgottenRichard Henderson1-0/+1
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-1/+1
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov1-0/+3
2013-07-29target-xtensa: add fallthrough markersMax Filippov1-0/+2
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-1/+3
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber1-1/+4
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-4/+4
2012-12-16exec: refactor cpu_restore_stateBlue Swirl1-12/+2
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov1-0/+57
2012-09-22target-xtensa: implement FP1 groupMax Filippov1-0/+47
2012-09-22target-xtensa: implement FP0 conversionsMax Filippov1-0/+37
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov1-0/+37
2012-09-22target-xtensa: add FP registersMax Filippov1-0/+13
2012-06-10target-xtensa: switch to AREG0-free modeMax Filippov1-95/+90
2012-06-09target-xtensa: update autorefill TLB entries conditionallyMax Filippov1-2/+2
2012-06-09target-xtensa: extract TLB entry setting methodMax Filippov1-4/+11
2012-06-09target-xtensa: flush TLB page for new MMU mappingMax Filippov1-0/+1
2012-04-14target-xtensa: fix tb invalidation for IBREAK and LOOPMax Filippov1-11/+18
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-5/+4
2012-04-14target-xtensa: Move helpers.h to helper.hLluís Vilanova1-1/+1
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber1-15/+15
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov1-0/+62
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov1-0/+38
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov1-15/+3
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl1-2/+3
2011-09-10target-xtensa: implement memory protection optionsMax Filippov1-6/+295
2011-09-10target-xtensa: implement interrupt optionMax Filippov1-0/+46
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov1-0/+26
2011-09-10target-xtensa: implement loop optionMax Filippov1-0/+20
2011-09-10target-xtensa: implement windowed registersMax Filippov1-0/+192
2011-09-10target-xtensa: implement exceptionsMax Filippov1-0/+29
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov1-0/+14
2011-09-10target-xtensa: implement disas_xtensa_insnMax Filippov1-0/+7
2011-09-10target-xtensa: add target stubsMax Filippov1-0/+52
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