index
:
peter/qemu
bdrv-getlength-conversion
block
block-dmg
block-dmg-2.2
block-dmg-2.3
block-dmg-2.3-v2
doc-updates
gdbstub-fixes
gtk-toggle-menubar
gtk-updates
logitech-unifying
logitech-unifying-2.2
master
serial-baud
slirp-fixes
usbdump-usbhid
QEMU hacking for Peter
Peter Wu
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-xtensa
/
translate.c
Age
Commit message (
Expand
)
Author
Files
Lines
2012-11-17
TCG: Use gen_opc_buf from context instead of global variable.
Evgeny Voevodin
1
-2
/
+2
2012-11-17
TCG: Use gen_opc_ptr from context instead of global variable.
Evgeny Voevodin
1
-3
/
+3
2012-11-10
target-xtensa: avoid using cpu_single_env
Blue Swirl
1
-5
/
+5
2012-10-06
target-xtensa: de-optimize EXTUI
Aurelien Jarno
1
-20
/
+2
2012-09-27
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
Richard Henderson
1
-1
/
+1
2012-09-22
target-xtensa: implement coprocessor context option
Max Filippov
1
-0
/
+38
2012-09-22
target-xtensa: implement FP1 group
Max Filippov
1
-1
/
+80
2012-09-22
target-xtensa: implement FP0 conversions
Max Filippov
1
-0
/
+48
2012-09-22
target-xtensa: implement FP0 arithmetic
Max Filippov
1
-1
/
+60
2012-09-22
target-xtensa: implement LSCX and LSCI groups
Max Filippov
1
-4
/
+54
2012-09-22
target-xtensa: add FP registers
Max Filippov
1
-7
/
+45
2012-09-21
target-xtensa: don't emit extra tcg_gen_goto_tb
Max Filippov
1
-1
/
+3
2012-09-21
target-xtensa: fix extui shift amount
Max Filippov
1
-3
/
+21
2012-07-28
target-xtensa: fix big-endian BBS/BBC implementation
Max Filippov
1
-2
/
+14
2012-06-10
target-xtensa: switch to AREG0-free mode
Max Filippov
1
-30
/
+34
2012-06-09
target-xtensa: fix CCOUNT for conditional branches
Max Filippov
1
-0
/
+2
2012-04-21
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Max Filippov
1
-1
/
+1
2012-04-14
target-xtensa: fix tb invalidation for IBREAK and LOOP
Max Filippov
1
-0
/
+2
2012-04-14
target-xtensa: Move helpers.h to helper.h
Lluís Vilanova
1
-3
/
+3
2012-03-14
target-xtensa: Don't overuse CPUState
Andreas Färber
1
-11
/
+11
2012-02-20
target-xtensa: add DBREAK data breakpoints
Max Filippov
1
-0
/
+30
2012-02-18
target-xtensa: add ICOUNT SR and debug exception
Max Filippov
1
-1
/
+48
2012-02-18
target-xtensa: implement instruction breakpoints
Max Filippov
1
-3
/
+65
2012-02-18
target-xtensa: add DEBUGCAUSE SR and configuration
Max Filippov
1
-0
/
+6
2012-02-18
target-xtensa: fetch 3rd opcode byte only when needed
Max Filippov
1
-1
/
+2
2011-11-02
target-xtensa: raise an exception for invalid and reserved opcodes
Max Filippov
1
-1
/
+6
2011-11-02
target-xtensa: mask out undefined bits of WINDOWSTART SR
Max Filippov
1
-1
/
+1
2011-10-16
target-xtensa: increase xtensa options accuracy
Max Filippov
1
-7
/
+7
2011-10-15
target-xtensa: implement MAC16 option
Max Filippov
1
-1
/
+134
2011-09-10
target-xtensa: implement boolean option
Max Filippov
1
-24
/
+85
2011-09-10
target-xtensa: implement memory protection options
Max Filippov
1
-5
/
+86
2011-09-10
target-xtensa: implement relocatable vectors
Max Filippov
1
-0
/
+1
2011-09-10
target-xtensa: implement CPENABLE and PRID SRs
Max Filippov
1
-0
/
+7
2011-09-10
target-xtensa: implement accurate window check
Max Filippov
1
-0
/
+110
2011-09-10
target-xtensa: implement interrupt option
Max Filippov
1
-10
/
+143
2011-09-10
target-xtensa: implement SIMCALL
Max Filippov
1
-1
/
+8
2011-09-10
target-xtensa: implement unaligned exception option
Max Filippov
1
-3
/
+44
2011-09-10
target-xtensa: implement extended L32R
Max Filippov
1
-4
/
+33
2011-09-10
target-xtensa: implement loop option
Max Filippov
1
-9
/
+68
2011-09-10
target-xtensa: implement windowed registers
Max Filippov
1
-9
/
+136
2011-09-10
target-xtensa: implement RST2 group (32 bit mul/div/rem)
Max Filippov
1
-1
/
+76
2011-09-10
target-xtensa: implement exceptions
Max Filippov
1
-5
/
+102
2011-09-10
target-xtensa: add PS register and access control
Max Filippov
1
-5
/
+24
2011-09-10
target-xtensa: implement CACHE group
Max Filippov
1
-1
/
+94
2011-09-10
target-xtensa: implement SYNC group
Max Filippov
1
-1
/
+30
2011-09-10
target-xtensa: mark reserved and TBD opcodes
Max Filippov
1
-1
/
+109
2011-09-10
target-xtensa: implement LSAI group
Max Filippov
1
-0
/
+89
2011-09-10
target-xtensa: implement shifts (ST1 and RST1 groups)
Max Filippov
1
-0
/
+242
2011-09-10
target-xtensa: implement RST3 group
Max Filippov
1
-0
/
+161
2011-09-10
target-xtensa: add special and user registers
Max Filippov
1
-2
/
+47
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