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path: root/target/arm/translate.h
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2018-04-10tcg: Introduce tcg_set_insn_start_paramRichard Henderson1-1/+1
2018-02-09target/arm: Add SVE state to TB->FLAGSRichard Henderson1-0/+2
2018-01-25target/arm: Mark disas_set_insn_syndrome inlineRichard Henderson1-1/+1
2017-12-29tcg: Dynamically allocate TCGOpsRichard Henderson1-5/+5
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-1/+0
2017-09-07Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'...Peter Maydell1-0/+1
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell1-0/+1
2017-09-06target/arm: [tcg] Port to generic translation frameworkLluís Vilanova1-7/+1
2017-09-06target/arm: [tcg] Port to translate_insnLluís Vilanova1-0/+1
2017-09-06target/arm: [tcg] Port to DisasContextBaseLluís Vilanova1-5/+6
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-9/+14
2017-09-06target/arm: Use DISAS_NORETURNRichard Henderson1-6/+2
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-2/+2
2017-07-17target/arm/translate.h: expand comment on DISAS_EXITAlex Bennée1-1/+4
2017-06-05target/arm: optimize indirect branchesEmilio G. Cota1-0/+4
2017-06-02arm: Add support for M profile CPUs having different MMU index semanticsPeter Maydell1-1/+1
2017-04-20arm: Implement M profile exception return properlyPeter Maydell1-0/+4
2017-04-20arm: Track M profile handler mode state in TB flagsPeter Maydell1-0/+1
2017-02-07target/arm: A32, T32: Create Instruction Syndromes for Data AbortsPeter Maydell1-0/+14
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+155