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2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson3-23/+66
The HW does not special-case r0, but the ABI specifies that r0 should contain 0. If we expose this fact to the optimizer, we can simplify a lot of the generated code. We must of course verify that r0==0, but that is trivial to do with a TB flag. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson5-35/+25
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson6-55/+39
The NPC SPR is really only supposed to be used for FPGA debugging. It contains the same contents as PC, unless one plays games. Follow the or1ksim implementation in flushing delayed branch state when it is changed. The PPC SPR need not be updated every instruction, merely when we exit the TB or attempt to read its contents. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson1-1/+5
This allows the tcg optimizer to see, and fold, all of the constants involved in a GOT base register load sequence. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Fix maddRichard Henderson4-61/+30
Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson1-0/+108
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson4-61/+80
Significantly simplifies the implementation of the use of MAC. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Implement msyncRichard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson1-32/+0
Not documented as disabled for user mode. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Set flags on helpersRichard Henderson1-12/+12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Use movcond where appropriateRichard Henderson1-14/+14
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson4-89/+78
This significantly streamlines carry and overflow production. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson7-74/+96
This avoids having to keep merging and extracting the flag from SR. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Invert the decoding in dec_calcRichard Henderson1-207/+95
Decoding the opcodes in the right order reduces by 100+ lines. Also, it happens to put the opcodes in the same order as Chapter 17. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson3-12/+18
Removes a call at execution time for overflow exceptions. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson5-314/+191
Fix incorrect overflow calculation. Move overflow exception check to a helper function, to eliminate inline branches. Remove some incorrect special casing of R0. Implement multiply inline. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson1-58/+40
The architecture manual is consistent in using "I" for signed fields and "K" for unsigned fields. Mirror that. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson1-24/+12
Avoids warnings from unused variables etc. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson7-8/+81
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Fix exception handling status registersStafford Horne1-0/+7
I am working on testing instruction emulation patches for the linux kernel. During testing I found these 2 issues: - sets DSX (delay slot exception) but never clears it - EEAR for illegal insns should point to the bad exception (as per openrisc spec) but its not This patch fixes these two issues by clearing the DSX flag when not in a delay slot and by setting EEAR to exception PC when handling illegal instruction exceptions. After this patch the openrisc kernel with latest patches boots great on qemu and instruction emulation works. Cc: qemu-trivial@nongnu.org Cc: openrisc@lists.librecores.org Signed-off-by: Stafford Horne <shorne@gmail.com> Message-Id: <20170113220028.29687-1-shorne@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson1-1/+1
This is in keeping with the toolchain and or1ksim. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée3-3/+3
We have never has the concept of global TLB entries which would avoid the flush so we never actually use this flag. Drop it and make clear that tlb_flush is the sledge-hammer it has always been. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> [DG: ppc portions] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2-8/+4
It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-10target-openrisc: Use clz and ctz opcodesRichard Henderson3-23/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth17-0/+3868
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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