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AgeCommit message (Expand)AuthorFilesLines
2017-01-18target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko1-14/+18
2017-01-18target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2-5/+4
2017-01-18target-sparc: fix immediate UA2005 trapsArtyom Tarasenko1-1/+1
2017-01-18target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko1-2/+5
2017-01-18target-sparc: implement UA2005 GL registerArtyom Tarasenko6-7/+58
2017-01-18target-sparc: implement UA2005 hypervisor trapsArtyom Tarasenko3-5/+39
2017-01-18target-sparc: hypervisor mode takes over nucleus modeArtyom Tarasenko2-3/+7
2017-01-18target-sparc: implement UltraSPARC-T1 Strand status ASRArtyom Tarasenko1-0/+11
2017-01-18target-sparc: implement UA2005 scratchpad registersArtyom Tarasenko3-0/+26
2017-01-18target-sparc: simplify replace_tlb_entry by using TTE_PGSIZEArtyom Tarasenko1-3/+2
2017-01-18target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor modeArtyom Tarasenko1-1/+2
2017-01-18target-sparc: add UltraSPARC T1 TLB #definesArtyom Tarasenko1-0/+4
2017-01-18target-sparc: add UA2005 TTE bit #definesArtyom Tarasenko1-0/+17
2017-01-18target-sparc: use explicit mmu register pointersArtyom Tarasenko2-12/+58
2017-01-18target-sparc: store cpu super- and hypervisor flags in TBArtyom Tarasenko2-5/+36
2017-01-18target-sparc: ignore MMU-faults if MMU is disabled in hypervisor modeArtyom Tarasenko2-2/+15
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée1-6/+6
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2-2/+4
2017-01-10target-sparc: Use ctpop helperRichard Henderson3-7/+1
2016-12-20Move target-* CPU file into a target/ folderThomas Huth21-0/+13805