summaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Collapse)AuthorFilesLines
2017-10-25ppc: Support Capstone in disas_set_infoRichard Henderson1-0/+6
Cc: qemu-ppc@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-25arm: Support Capstone in disas_set_infoRichard Henderson1-3/+18
Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-25i386: Support Capstone in disas_set_infoRichard Henderson1-0/+7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-25disas: Remove unused flags argumentsRichard Henderson19-22/+19
Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-25target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLYRichard Henderson1-2/+7
This matches translator behaviour in arm_lduw_code. Fixes: https://bugs.launchpad.net/qemu/+bug/1724485 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-25target/arm: Move BE32 disassembler fixupRichard Henderson1-19/+0
The Capstone disassembler has its own big-endian fixup. Doing this twice does not work, of course. Move our current fixup from target/arm/cpu.c to disas/arm.c. This makes read_memory_inner_func unused and can be removed. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-25target/ppc: Convert to disas_set_info hookRichard Henderson2-4/+22
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-25target/i386: Convert to disas_set_info hookRichard Henderson2-7/+13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne4-5/+5
In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec which has a separate timer counter per core, but it seems the most simple way to keep each clock in sync. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-10-21target/openrisc: Make coreid and numcores variableStafford Horne1-2/+3
Previously coreid and numcores were hard coded as 0 and 1 respectively as OpenRISC QEMU did not have multicore support. Multicore support is now being added so these registers need to have configured values. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-10-20s390x/tcg: low-address protection supportDavid Hildenbrand3-45/+62
This is a neat way to implement low address protection, whereby only the first 512 bytes of the first two pages (each 4096 bytes) of every address space are protected. Store a tec of 0 for the access exception, this is what is defined by Enhanced Suppression on Protection in case of a low address protection (Bit 61 set to 0, rest undefined). We have to make sure to to pass the access address, not the masked page address into mmu_translate*(). Drop the check from testblock. So we can properly test this via kvm-unit-tests. This will check every access going through one of the MMUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171016202358.3633-3-david@redhat.com> [CH: restored error message for access register mode] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: refactor error handling for MSCH handlerHalil Pasic1-19/+4
Simplify the error handling of the MSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-8-pasic@linux.vnet.ibm.com> [CH: fix return code for fctl != 0] Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: refactor error handling for HSCH handlerHalil Pasic1-19/+4
Simplify the error handling of the HSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-7-pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: refactor error handling for CSCH handlerHalil Pasic1-10/+4
Simplify the error handling of the CSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-6-pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: refactor error handling for XSCH handlerHalil Pasic1-19/+4
Simplify the error handling of the XSCH. Let the code detecting the condition tell (in a less ambiguous way) how it's to be handled. No changes in behavior. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-5-pasic@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: improve error handling for SSCH and RSCHHalil Pasic1-46/+7
Simplify the error handling of the SSCH and RSCH handler avoiding arbitrary and cryptic error codes being used to tell how the instruction is supposed to end. Let the code detecting the condition tell how it's to be handled in a less ambiguous way. It's best to handle SSCH and RSCH in one go as the emulation of the two shares a lot of code. For passthrough this change isn't pure refactoring, but changes the way kernel reported EFAULT is handled. After clarifying the kernel interface we decided that EFAULT shall be mapped to unit exception. Same goes for unexpected error codes and absence of required ORB flags. Signed-off-by: Halil Pasic <pasic@linux.vnet.ibm.com> Message-Id: <20171017140453.51099-4-pasic@linux.vnet.ibm.com> Tested-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> [CH: cosmetic changes] Reviewed-by: Dong Jia Shi <bjsdjshi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: move s390x_new_cpu() into board codeIgor Mammedov2-21/+0
s390-virtio-ccw.c is the sole user of s390x_new_cpu(), so move this helper there. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1508253203-119237-1-git-send-email-imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x: fix cpu object referrence leak in s390x_new_cpu()Igor Mammedov1-1/+1
object_new() returns cpu with refcnt == 1 and after realize refcnt == 2*. s390x_new_cpu() as an owner of the first refcnt should have released it on exit in both cases (on error and success) to avoid it leaking. Do so for both cases. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1508247680-98800-2-git-send-email-imammedo@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20target/s390x: special handling when starting a CPU with WAIT PSWDavid Hildenbrand2-3/+14
When we try to start a CPU with a WAIT PSW, we have to take care that TCG will actually try to continue executing instructions. We must therefore really only unhalt the CPU if we don't have a WAIT PSW. Also document the special order for restart interrupts, which load a new PSW and change the state to operating. To keep KVM working, simply don't have a look at the WAIT bit when loading the PSW. Otherwise the behavior of a restart interrupt when a CPU stopped would be changed. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-31-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: refactor stfl(e) to use s390_get_feat_block()David Hildenbrand2-39/+29
Refactor it to use s390_get_feat_block(). Directly write into the mapped lowcore with stfl and make sure it is really only compiled if needed. While at it, add an alignment check for STFLE and avoid potential_page_fault() by properly restoring the CPU state. Due to s390_get_feat_block(), we will now also indicate the "Configuration-z-architectural-mode", which is with new SIGP code the right thing to do. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-30-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: unlock NMIDavid Hildenbrand1-5/+0
Nothing hindering us anymore from unlocking the restart code (used for NMI). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-29-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/cpumodel: allow to enable SENSE RUNNING STATUS for qemuDavid Hildenbrand1-0/+1
As we properly implement it, allow to enable it. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-28-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: switch to new SIGP handling codeDavid Hildenbrand4-40/+11
This effectively enables experimental SMP support. Floating interrupts are still a mess, so allow it but print a big warning. There also seems to be a problem with CPU hotplug (after the main loop started). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-27-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [CH: changed insn-data.def as pointed out by Richard] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: flush the tlb on SIGP SET PREFIXDavid Hildenbrand1-0/+1
Thanks to Aurelien Jarno for doing this in his prototype. We can flush the whole TLB as this should happen really rarely. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-26-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: implement STOP and RESET interrupts for TCGDavid Hildenbrand6-6/+51
Implement them like KVM implements/handles them. Both can only be triggered via SIGP instructions. RESET has (almost) the lowest priority if the CPU is running, and the highest if the CPU is STOPPED. This is handled in SIGP code already. On delivery, we only have to care about the "CPU running" scenario. STOP is defined to be delivered after all other interrupts have been delivered. Therefore it has the actual lowest priority. As both can wake up a CPU if sleeping, indicate them correctly to external code (e.g. cpu_has_work()). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-25-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: implement SIGP CONDITIONAL EMERGENCY SIGNALDavid Hildenbrand2-0/+38
Mostly analogous to the kernel/KVM version (so I assume the checks are correct :) ). As a preparation for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-24-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: implement SIGP EMERGENCY SIGNALDavid Hildenbrand1-0/+15
As preparation for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-23-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: implement SIGP EXTERNAL CALLDavid Hildenbrand1-2/+23
As preparation for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-22-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: implement SIGP SENSEDavid Hildenbrand1-0/+29
Add it as preparation for TCG. Sensing could later be done completely lockless. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-21-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: implement SIGP SENSE RUNNING STATUSDavid Hildenbrand2-0/+27
Preparation for TCG, for KVM is this is completely handled in the kernel. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-20-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/kvm: factor out actual handling of STOP interruptsDavid Hildenbrand3-8/+16
For KVM, the KVM module decides when a STOP can be performed (when the STOP interrupt can be processed). Factor it out so we can use it later for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-19-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/kvm: factor out SIGP code into sigp.cDavid Hildenbrand9-359/+385
We want to use the same code base for TCG, so let's cleanly factor it out. The sigp mutex is currently not really needed, as everything is protected by the iothread mutex. But this could change later, so leave it in place and initialize it properly from common code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/kvm: drop two debug printsDavid Hildenbrand1-2/+0
Preparation for moving it out of kvm.c. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/kvm: factor out storing of adtl CPU statusDavid Hildenbrand3-29/+31
Called from SIGP code to be factored out, so let's move it. Add a FIXME for TCG code in the future. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/kvm: factor out storing of CPU statusDavid Hildenbrand3-66/+65
Factor it out into s390_store_status(), to be used also by TCG later on. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-14-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/kvm: generalize SIGP stop and restart interrupt injectionDavid Hildenbrand5-12/+53
Preparation for factoring it out into !kvm code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/kvm: pass ipb directly into handle_sigp()David Hildenbrand1-3/+3
No need to pass kvm_run. Pass parameters alphabetically ordered. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20target/s390x: interpret PSW_MASK_WAIT only for TCGDavid Hildenbrand1-1/+2
KVM handles the wait PSW itself and triggers a WAIT ICPT in case it really wants to sleep (disabled wait). This will later allow us to change the order of loading a restart interrupt and setting a CPU to OPERATING on SIGP RESTART without changing KVM behavior. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-11-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: handle WAIT PSWs during interrupt injectionDavid Hildenbrand1-0/+6
If we encounter a WAIT PSW, we have to halt immediately. Using cpu_loop_exit() at this point feels wrong. Simply leaving cs->exception_index set doesn't result in an immediate stop. This is also necessary to properly handle SIGP STOP interrupts later. The CPU_INTERRUPT_HALT will be processed immediately and properly set the CPU to halted (also resetting cs->exception_index to EXCP_HLT) Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-10-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20target/s390x: factor out handling of WAIT PSW into s390_handle_wait()David Hildenbrand3-19/+23
This will now also detect crashes under TCG. We can directly use cpu->env.psw.addr instead of kvm_run, as we do a cpu_synchronize_state(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: a CPU cannot switch state due to an interruptDavid Hildenbrand1-1/+0
Going to OPERATING here looks wrong. A CPU should even never be !OPERATING at this point. Unhalting will already be done in cpu_handle_halt() if there is work, so we can drop this statement completely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: STOPPED cpus can never wake upDavid Hildenbrand1-0/+6
Interrupts can't wake such CPUs up. SIGP from other CPUs has to be used to toggle the state. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: take care of external interrupt subclassesDavid Hildenbrand4-13/+50
We can now let go of INTERRUPT_EXT. When cr0 changes, we have to revalidate if we now have a pending external interrupt, just like when the PSW (or SYSTEM MASK only) changes. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-6-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: rework checking for deliverable interruptsDavid Hildenbrand4-17/+62
Currently, enabling/disabling of interrupts is not really supported. Let's improve interrupt handling code by explicitly checking for deliverable interrupts only. This is the first step. Checking for external interrupt subclasses will be done next. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-5-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: injection of emergency signals and external callsDavid Hildenbrand4-2/+50
Preparation for new TCG SIGP code. Especially also prepare for indicating that another external call is already pending. Take care of interrupt priority. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-4-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: cleanup service interrupt injectionDavid Hildenbrand5-38/+10
There are still some leftovers from old virtio interrupts in there. Most importantly, we don't have to queue service interrupts anymore. Just like KVM, we can simply multiplex the SCLP service interrupts and avoid the queue. Also, now only valid parameters/cpu_addr will be stored on service interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-3-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20s390x/tcg: turn INTERRUPT_EXT into a maskDavid Hildenbrand5-47/+61
External interrupts are currently all handled like floating external interrupts, they are queued. Let's prepare for a split of floating and local interrupts by turning INTERRUPT_EXT into a mask. While we can have various floating external interrupts of one kind, there is usually only one (or a fixed number) of the local external interrupts. So turn INTERRUPT_EXT into a mask and properly indicate the kind of external interrupt. Floating interrupts will have to moved out of one CPU instance later once we have SMP support. The only floating external interrupts used right now are SERVICE interrupts, so let's use that name. Following patches will clean up SERVICE interrupt injection. This get's rid of the ugly special handling for cpu timer and clock comparator interrupts. And we really only store the parameters as defined by the PoP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170928203708.9376-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20S390: use g_new() family of functionsMarc-André Lureau2-7/+7
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: more changes in hw/s390x/css.c, added target/s390x/cpu_models.c] Message-Id: <20171006235023.11952-27-f4bug@amsat.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-19Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell3-110/+149
* TCG 8-byte atomic accesses bugfix (Andrew) * Report disk rotation rate (Daniel) * Report invalid scsi-disk block size configuration (Mark) * KVM and memory API MemoryListener fixes (David, Maxime, Peter Xu) * x86 CPU hotplug crash fix (Igor) * Load/store API documentation (Peter Maydell) * Small fixes by myself and Thomas * qdev DEVICE_DELETED deferral (Michael) # gpg: Signature made Wed 18 Oct 2017 10:56:24 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (29 commits) scsi: reject configurations with logical block size > physical block size qdev: defer DEVICE_DEL event until instance_finalize() Revert "qdev: Free QemuOpts when the QOM path goes away" qdev: store DeviceState's canonical path to use when unparenting qemu-pr-helper: use new libmultipath API watch_mem_write: implement 8-byte accesses notdirty_mem_write: implement 8-byte accesses memory: reuse section_from_flat_range() kvm: simplify kvm_align_section() kvm: region_add and region_del is not called on updates kvm: fix error message when failing to unregister slot kvm: tolerate non-existing slot for log_start/log_stop/log_sync kvm: fix alignment of ram address memory: call log_start after region_add target/i386: trap on instructions longer than >15 bytes target/i386: introduce x86_ld*_code tco: add trace events docs/devel/loads-stores.rst: Document our various load and store APIs nios2: define tcg_env build: remove CONFIG_LIBDECNUMBER ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-19Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20171018' ↵Peter Maydell3-3/+15
into staging Linux-user updates for Qemu 2.11 # gpg: Signature made Wed 18 Oct 2017 13:20:14 BST # gpg: using RSA key 0xB44890DEDE3C9BC0 # gpg: Good signature from "Riku Voipio <riku.voipio@iki.fi>" # gpg: aka "Riku Voipio <riku.voipio@linaro.org>" # Primary key fingerprint: FF82 03C8 C391 98AE 0581 41EF B448 90DE DE3C 9BC0 * remotes/riku/tags/pull-linux-user-20171018: linux-user: Fix TARGET_MTIOCTOP/MTIOCGET/MTIOCPOS values linux-user/main: support dfilter linux-user: Fix target FS_IOC_GETFLAGS and FS_IOC_SETFLAGS numbers linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31 linux-user: Tidy and enforce reserved_va initialization tcg: Fix off-by-one in assert in page_set_flags linux-user: Allow -R values up to 0xffff0000 for 32-bit ARM guests linux-user: remove duplicate break in syscall target/m68k,linux-user: manage FP registers in ucontext linux-user: fix O_TMPFILE handling Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.1 (git 2.18.0) at 2024-07-14 08:08:10 +0000