summaryrefslogtreecommitdiff
path: root/tcg/arm/tcg-target.h
AgeCommit message (Expand)AuthorFilesLines
2013-10-12tcg-arm: Convert to new ldst opcodesRichard Henderson1-1/+1
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-0/+2
2013-09-02tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson1-5/+4
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+2
2013-07-09tcg-arm: Make use of conditional availability of opcodes for divideRichard Henderson1-6/+8
2013-07-09tcg-arm: Don't implement remRichard Henderson1-2/+1
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson1-0/+2
2013-04-27tcg-arm: Implement division instructionsRichard Henderson1-1/+6
2013-04-27tcg-arm: Implement deposit for armv7Richard Henderson1-1/+4
2013-04-27tcg-arm: Use bic to implement and with constantRichard Henderson1-2/+0
2013-02-23tcg-arm: Implement muls2_i32Richard Henderson1-1/+1
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+1
2012-12-19janitor: add guards to headersPaolo Bonzini1-0/+3
2012-10-19Merge branch 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoi...Aurelien Jarno1-2/+0
2012-10-17tcg/arm: Implement movcond_i32Peter Maydell1-1/+1
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell1-2/+0
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+1
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl1-1/+0
2012-03-03w64: Change data type of parameters for flush_icache_rangeStefan Weil1-1/+2
2012-01-10tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointerPeter Maydell1-1/+1
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-14/+16
2010-04-19tcg/arm: add bswap opsAurelien Jarno1-2/+2
2010-04-19tcg/arm: add ext16u opAurelien Jarno1-2/+2
2010-04-19tcg/arm: add rotation opsAurelien Jarno1-1/+1
2010-04-19tcg/arm: align 64-bit arguments in function callsAurelien Jarno1-0/+1
2010-04-19tcg/arm: explicitely list clobbered/reserved regsAurelien Jarno1-1/+2
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
2010-03-14tcg/arm: use helpers for divu/remuAurelien Jarno1-1/+0
2010-03-14tcg: add div/rem 32-bit helpersAurelien Jarno1-0/+1
2010-03-13tcg/arm: implement andc opAurelien Jarno1-1/+1
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno1-14/+5
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-0/+14
2009-08-22ARM back-end: Add TCG notLaurent Desnogues1-0/+1
2009-07-18this patch improves the ARM back-end in the following way:Laurent Desnogues1-0/+2
2009-07-17Userspace guest address offsettingPaul Brook1-0/+2
2009-07-17ARM host fixesPaul Brook1-3/+3
2009-03-13tcg: rename bswap_i32/i64 functionsaurel321-1/+1
2009-03-08Prune unused TCG_AREGsblueswir11-1/+0
2008-12-01Use libgcc __clear_cache to clean icache, when available.balrog1-0/+5
2008-05-23Define TCG_TARGET_CALL_STACK_OFFSET on arm.balrog1-2/+3
2008-05-20Implement neg_i32, clean-up.balrog1-0/+2
2008-05-19ARM host support for TCG targets.balrog1-0/+73
generated by cgit v1.2.1 (git 2.18.0) at 2024-05-15 02:23:32 +0000