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2010-04-19tcg/arm: don't try to load constants using pcAurelien Jarno1-7/+0
There is statistically almost 0 chances to use this code, so remove it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: optimize register allocation orderAurelien Jarno1-5/+5
The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: fix argument alignment in qemu_st64Aurelien Jarno1-9/+10
64-bit arguments should be aligned on an even register as specified by the "Procedure Call Standard for the ARM Architecture". Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: remove useless register tests in qemu_ld/stAurelien Jarno1-20/+10
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the constraints. Don't check if they equals these registers. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: bswap arguments in qemu_ld/st if neededAurelien Jarno1-69/+159
On big endian targets, data arguments of qemu_ld/st ops have to be byte swapped. Two temporary registers are needed for qemu_st to do the bswap. r0 and r1 are used in system mode, do the same in user mode, which implies reworking the constraints. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: use ext* ops in qemu_ldAurelien Jarno1-18/+12
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: remove conditional argument for qemu_ld/stAurelien Jarno1-51/+49
While it make sense to pass a conditional argument to tcg_out_*() functions as the ARM architecture allows that, it doesn't make sense for qemu_ld/st functions. These functions use comparison instructions and conditional execution already, so it is not possible to use a second level of conditional execution. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add bswap opsAurelien Jarno2-2/+44
Add an bswap16 and bswap32 ops, either using the rev and rev16 instructions on ARMv6+ or shifts and logical operations on previous ARM versions. In both cases the result use less instructions than the pure TCG version. These ops are also needed by the qemu_ld/st functions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add ext16u opAurelien Jarno2-20/+50
Add an ext16u op, either using the uxth instruction on ARMv6+ or two shifts on previous ARM versions. In both cases the result use the same number or less instructions than the pure TCG version. Also move all sign extension code to separate functions, so that they can be reused in other parts of the code. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add rotation opsAurelien Jarno2-1/+20
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: use the blx instruction when possibleAurelien Jarno1-4/+12
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: sxtb and sxth are available starting with ARMv6Aurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: add variables to define the allowed instructions setAurelien Jarno1-39/+84
Use a set of variables to define the allowed ARM instructions, depending on the __ARM_ARCH_*__ GCC defines. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: align 64-bit arguments in function callsAurelien Jarno1-0/+1
As specified by the "Procedure Call Standard for the ARM Architecture". Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: replace integer values by registers enumAurelien Jarno1-109/+124
The TCG ARM backends uses integer values to refer to both immediate values and register number. This makes the code difficult to read. The patch below replaces all (if I haven't miss any ;-) integer values representing register number by TCG_REG_* enum values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: remove store signed functionsAurelien Jarno1-62/+10
Store signed functions doesn't make sense, and are not used. Remove them. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: explicitely list clobbered/reserved regsAurelien Jarno2-5/+11
Instead of writing very compact code, declare all registers that are clobbered or reserved one by one. This makes the code easier to read. Also declare all the 16 registers to TCG, and mark pc as reserved. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-19tcg/arm: remove SAVE_LR codeAurelien Jarno1-43/+0
There is no need to save the LR register (r14) before a call to a subroutine. According to the "Procedure Call Standard for the ARM Architecture", it is the job of the callee to save this register. Moreover, this register is already saved in the prologue/epilogue. This patch removes the disabled SAVE_LR code, as there is no need to reenable later. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-28tcg/arm: Replace qemu_ld32u (left over from previous commit)Stefan Weil1-1/+1
Commit 86feb1c860dc38e9c89e787c5210e8191800385e did not change all occurrences of INDEX_op_qemu_ld32u for tcg/arm. Please note that I could not test this patch (I have currently no arm system available). Cc: Richard Henderson <rth@twiddle.net> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-2/+2
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg/arm: don't save/restore r7 in prologue/epilogueAurelien Jarno1-6/+6
There is no need to save r7, it is used to store the address of the env structure and is not modified by GCC. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-20tcg/arm: fix load/store definitions for 32-bit targetsAurelien Jarno1-0/+14
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg/arm: use helpers for divu/remuAurelien Jarno2-95/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-14tcg: add div/rem 32-bit helpersAurelien Jarno1-0/+1
Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg/arm: implement andc opAurelien Jarno2-1/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg/arm: correctly save/restore registers in prologue/epilogueAurelien Jarno1-4/+7
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crashes on ARM hosts. This is not a bug of this commit, but a latent bug revealed by this commit. The TCG code is called through a procedure call using the prologue and epilogue code. This code does not save and restore enough registers. The "Procedure Call Standard for the ARM Architecture" says: A subroutine must preserve the contents of the registers r4-r8, r10,  r11 and SP (and r9 in PCS variants that designate r9 as v6). The current code only saves and restores r9 to r11, and misses r4 to r8. The patch fixes that by saving r4 to r12. Theoretically there is no need to save and restore r12, but an even number of registers have to be saved as per EABI. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-12Remove TLB from userspacePaul Brook1-0/+2
Remove TLB from userspace CPU structure. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-02tcg/arm: merge the two sets of #define for optional opsAurelien Jarno1-14/+5
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02tcg/arm: accept immediate arguments for brcond/setcondAurelien Jarno1-6/+20
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02Add a missing breakAndrzej Zaborowski1-0/+1
2010-03-02tcg/arm: implement setcond2Aurelien Jarno1-0/+11
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: implement setcondAurelien Jarno1-0/+9
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-03-02tcg/arm: fix div2/divu2Aurelien Jarno1-6/+24
When restoring register values, increase the stack register for skipped values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-0/+14
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-26ARM back-end: Use sxt[bh] instructions for ext{8, 6}sLaurent Desnogues1-0/+10
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-25Suppress some variants of English in commentsStefan Weil1-2/+2
Replace surpress, supress by suppress. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-08-25ARM back-end: Fix encode_immLaurent Desnogues1-0/+2
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-22ARM back-end: Handle all possible immediates for ALU opsLaurent Desnogues1-5/+32
this patch handles all possible constants for immediate operand of ALU ops. I'm not very satisfied by the implementation. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-22ARM back-end: Add TCG notLaurent Desnogues2-0/+6
this patch: - implements TCG not. Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-27rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela1-1/+1
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-18this patch improves the ARM back-end in the following way:Laurent Desnogues2-7/+37
- use movw/movt to load immediate values for ARMv7-A - implement add/sub/and/or/xor with immediate (only 8-bit) Laurent Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-17Userspace guest address offsettingPaul Brook2-2/+34
Re-implement GUEST_BASE support. Offset guest ddress space by default if the guest binary contains regions below the host mmap_min_addr. Implement support for i386, x86-64 and arm hosts. Signed-off-by: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-17ARM host fixesPaul Brook2-4/+4
Minor TCG cleanups and warning fixes for ARM hosts. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-03-13tcg: rename bswap_i32/i64 functionsaurel321-1/+1
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10tcg-arm: fix qemu_ld64aurel321-2/+7
Emulating fldl on arm doesn't seem to work too well. It's the way qemu_ld64 is translated to arm instructions. tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4); Consider case where data_reg==0, data_reg2==1, and addr_reg==0. First load overwrited addr_reg. So let's put an if (data_ref==addr_reg). (Pablo Virolainen) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6808 c046a42c-6fe2-441c-8c8c-71466251a162
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