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2014-06-04tcg: Remove TCG_TARGET_HAS_new_ldstRichard Henderson1-2/+0
Since all backends have been converted, remove the compatibility code. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-06-04tcg-i386: Fix win64 qemu storeRichard Henderson1-1/+2
The first non-register argument isn't placed at offset 0. Cc: qemu-stable@nongnu.org Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-28tcg-i386: Make debug_frame constRichard Henderson1-21/+17
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Remove unreachable code in tcg_out_op and op_defsRichard Henderson1-19/+5
The INDEX_op_call case has just been obsoleted; the mov and movi cases have not been reachable for years. Attempt to document this both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT. Because of the TCG_OPF_NOT_PRESENT change, this must be done for all targets in a single commit. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-i386: Rename tcg_out_calli to tcg_out_callRichard Henderson1-3/+3
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg-i386: Define TCG_TARGET_INSN_UNIT_SIZERichard Henderson2-24/+26
And use tcg pointer differencing functions as appropriate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-05-12tcg: Avoid undefined behaviour patching code at unaligned addressesPeter Maydell1-6/+6
To avoid C undefined behaviour when patching generated code, provide wrappers tcg_patch8/16/32/64 which use the usual memcpy trick, and use them in the i386 backend. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-28tcg: Add INDEX_op_trunc_shr_i32Richard Henderson1-0/+1
Let the backend do something special for truncation. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Use HOST_WORDS_BIGENDIANRichard Henderson1-2/+0
Instead of rolling a local TCG_TARGET_WORDS_BIGENDIAN. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Add TCGType parameter to tcg_target_const_matchRichard Henderson1-1/+1
Most 64-bit targets need to be able to ignore the high bits of a TCG_TYPE_I32 value. Suggested-by: Stuart Brady <sdb@zubnet.me.uk> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-04-18tcg: Fix warning (1 bit signed bitfield entry) and replace int by boolStefan Weil1-3/+3
Static code analyzers complain about signed bitfields with only a single bit. is_ld is used as a boolean value, so make it bool. ppc64 already used bool for the 2nd argument is_ld of the local function add_qemu_ldst_label. Modify all other TCG targets to do follow this example. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-02-21tcg/i386: Fix build for systems without working cpuid.h (MacOSX, Win32)Peter Maydell1-1/+3
Win32 doesn't have a cpuid.h, and MacOSX may have one but without the __cpuid() function we use, which means that commit 9d2eec20 broke the build for those platforms. Fix this by tightening up our configure cpuid.h check to test that the functions we need are present, and adding some missing #ifdef guards in tcg/i386/tcg-target.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-17tcg/i386: Use SHLX/SHRX/SARX instructionsRichard Henderson1-11/+50
These three-operand shift instructions do not require the shift count to be placed into ECX. This reduces the number of mov insns required, with the mere addition of a new register constraint. Don't attempt to get rid of the matching constraint, as that's impossible to manipulate with just a new constraint. In addition, constant shifts still need the matching constraint. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-02-17tcg/i386: Use ANDN instructionRichard Henderson2-13/+45
Note that the optimizer cannot simplify ANDC X,Y,C to AND X,Y,~C so we must handle constants in the implementation of andc. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-02-17tcg/i386: Add tcg_out_vex_modrmRichard Henderson1-3/+38
Prepare for emitting BMI insns which require VEX encoding. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-02-17tcg/i386: Move TCG_CT_CONST_* to tcg-target.cRichard Henderson2-3/+4
These are not needed by users of tcg-target.h. No need to recompile when we adjust them. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-25tcg/i386: cleanup useless #ifdefAurelien Jarno1-2/+0
TCG_TARGET_HAS_movcond_i32 is always defined to 1 in tcg-target.h, so remove the corresponding #ifdef #endif sequence, left from a previous refactoring. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-25tcg/i386: use movbe instruction in qemu_ldst routinesAurelien Jarno1-37/+80
The movbe instruction has been added on some Intel Atom CPUs and on recent Intel Haswell CPUs. It allows to load/store a value and at the same time bswap it. This patch detects the avaibility of this instruction and when available use it in the qemu load/store routines in replacement of load/store + bswap. Note that for 16-bit unsigned loads, movbe + movzw is basically the same as movzw + bswap, so the patch doesn't touch this case. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [RTH: Reduced the number of conditionals using "movop".] Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-25tcg/i386: add support for three-byte opcodesAurelien Jarno1-8/+16
Add support for three-byte opcodes, starting with the 0x0f 0x38 prefix. Use P_EXT38 as the new constant, and shift all other constants so that P_EXT and P_EXT38 have neighbouring values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [RTH: Changed the name from P_EXT2 to P_EXT38.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-25tcg/i386: remove hardcoded P_REXW valueAurelien Jarno1-1/+1
P_REXW is defined has a constant at the beginning of i386/tcg-target.c, but the corresponding bit is later used in a harcoded way, which defeat the purpose of a constant. Fix that by using a conditional expression operator instead of a shift. On x86 this actually makes the code slightly smaller as GCC does in practice (opc >> 8) & 8 instead of (opc & 0x800) >> 8 so the constants are smaller to load. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-12-21tcg/i386: fix a commentAurelien Jarno1-1/+1
The comments apply to 8-bit stores, not 8-byte stores. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-10-12tcg-i386: Support new ldst opcodesRichard Henderson2-90/+51
No support for helpers with non-default endianness yet, but good enough to test the opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-i386: Remove "cb" output restriction from qemu_st8 for i386Richard Henderson1-2/+8
Once we form a combined qemu_st_i32 opcode, we won't be able to have separate constraints based on size. This one is fairly easy to work around, since eax is available as a scratch register. When storing variable data, this tends to merely exchange one mov for another. E.g. -: mov %esi,%ecx ... -: mov %cl,(%edx) +: mov %esi,%eax +: mov %al,(%edx) Where we do have a regression is when storing constant data, in which we may load the constant into edi, when only ecx/ebx ought to be used. The proper way to recover this regression is to allow constants as arguments to qemu_st_i32, so that we never load the constant data into a register at all, must less the wrong register. TBD. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-i386: Tidy softmmu routinesRichard Henderson1-249/+208
Pass two TCGReg to tcg_out_tlb_load, rather than idx+args. Move ldst_optimization routines just below tcg_out_tlb_load to avoid the need for forward declarations. Use TCGReg enum in preference to int where apprpriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-i386: Use TCGMemOp within qemu_ldst routinesRichard Henderson1-64/+59
Step one in the transition, with constants passed down from tcg_out_op. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-0/+2
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add tcg-be-ldst.hRichard Henderson1-27/+3
Move TCGLabelQemuLdst and related stuff out of tcg.h. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg-i386: Make use of zero-extended memory helper routinesRichard Henderson1-9/+6
For 8 and 16-bit unsigned loads, rely on the zero-extension from the helper and use a smaller 32-bit move insn. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Introduce zero and sign-extended versions of load helpersRichard Henderson1-3/+3
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02exec: Split softmmu_defs.hRichard Henderson1-3/+0
The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg-i386: Don't perform GETPC adjustment in TCG codeRichard Henderson1-19/+14
Since we now perform it inside the helper, no need to do it here. This also lets us perform a tail-call from the store slow path to the helper. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg-i386: Adjust tcg_out_tlb_load for x32Richard Henderson1-14/+27
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg-i386: Use intptr_t appropriatelyRichard Henderson1-22/+19
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_out_ld/st offset to intptr_tRichard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change relocation offsets to intptr_tRichard Henderson1-1/+1
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Allow TCG_TARGET_REG_BITS to be specified independantlyRichard Henderson1-4/+6
There are several hosts for which it would be useful to use the available 64-bit registers in a 32-bit pointer environment. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson1-2/+1
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+4
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-08-26tcg-i386: Use new return-argument ld/st helpersRichard Henderson1-56/+47
Discontinue the jump-around-jump-to-jump scheme, trading it for a single immediate move instruction. The two extra jumps always consume 7 bytes, whereas the immediate move is either 5 or 7 bytes depending on where the code_gen_buffer gets located. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-08-26tcg-i386: Tidy qemu_ld/st slow pathRichard Henderson1-91/+74
Use existing stack space for arguments; don't push/pop. Use less ifdefs and more C ifs. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-08-26tcg-i386: Try pc-relative lea for constant formationRichard Henderson1-5/+20
Use a 7 byte lea before the ultimate 10 byte movq. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-08-26tcg-i386: Add and use tcg_out64Richard Henderson1-2/+1
No point in splitting the write into 32-bit pieces. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame sizeRichard Henderson1-3/+3
We can check the condition at compile time, rather than run time. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Move the CIE and FDE header definitions to common codeRichard Henderson1-26/+13
These will necessarily be the same layout for all hosts. This limits the amount of boilerplate required to implement jit debug for a host. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-05tcg: Remove redundant tcg_target_init checksRichard Henderson1-6/+0
We've got a compile-time check for the condition in exec/cpu-defs.h. Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: liguang <lig.fnst@cn.fujitsu.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23tcg-i386: Implement multiword arithmetic opsRichard Henderson2-17/+26
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add 64-bit multiword arithmetic operationsRichard Henderson1-0/+3
Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg-i386: Always implement 32-bit multiword opsRichard Henderson2-12/+13
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson1-0/+4
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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