summaryrefslogtreecommitdiff
path: root/tcg/ppc64/tcg-target.h
AgeCommit message (Collapse)AuthorFilesLines
2013-10-12tcg-ppc64: Support new ldst opcodesRichard Henderson1-1/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-0/+2
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg-ppc64: Implement muluh, mulshRichard Henderson1-4/+4
Using these instead of mulu2 and muls2 lets us avoid having to argument overlap analysis in the backend. Normal register allocation will DTRT. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+4
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-ppc64: Don't implement remRichard Henderson1-2/+2
Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson1-0/+2
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement mulu2/muls2_i64Richard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement add2/sub2_i64Richard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement movcondRichard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement depositRichard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement compound logicalsRichard Henderson1-10/+10
Mostly copied from the ppc32 port. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement bswap64Richard Henderson1-1/+1
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement bswap16 and bswap32Richard Henderson1-4/+4
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Implement rotatesRichard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use automatic implementation of ext32u_i64Richard Henderson1-3/+3
The enhancements to and immediate obviate this. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Improve and_i32 with constantRichard Henderson1-2/+4
Use RLWINM Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add 64-bit multiword arithmetic operationsRichard Henderson1-0/+3
Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-19janitor: add guards to headersPaolo Bonzini1-0/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell1-1/+0
GUEST_BASE support is now supported by all TCG backends, and is now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE define (set by every backend) and the error if it is unset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+2
Implemented with setcond if the target does not provide the optional opcode. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
Most targets did not name the enum; tci used TCGRegister. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
It is now declared for all tcg targets in tcg.h, so the tcg target specific declarations are redundant. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-22tcg/ppc64: fix 16/32 mixupmalc1-2/+2
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22tcg/ppc64: implement not_i32/64 and ext32u_i64malc1-3/+3
Signed-off-by: malc <av1474@comtv.ru>
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-33/+35
By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-16tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson1-0/+1
Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-22tcg/ppc64: Use C90 style commentsmalc1-18/+18
Signed-off-by: malc <av1474@comtv.ru>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-3/+22
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-18PPC 32/64 GUEST_BASE supportmalc1-0/+2
Signed-off-by: malc <av1474@comtv.ru>
2009-03-08Prune unused TCG_AREGsblueswir11-1/+0
Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10Introduce and use cache-utils.[ch]malc1-21/+0
Thanks to Segher Boessenkool and Holis Blanchard. AIX and Darwin cache inquiry: http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html Auxiliary vectors: http://manugarg.googlepages.com/aboutelfauxiliaryvectors git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-24Use proper value for TCG_TARGET_CALL_STACK_OFFSETmalc1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4941 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23Provide extNs_M instructionsmalc1-0/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23Preliminary PPC64/Linux host supportmalc1-0/+100
ppc64.ld from Heikki Lindholm's patch http://marc.info/?l=qemu-devel&m=114086179024634&w=2 Issues: x86_64 tripple faults shortly after decompressing the kernel No immediate versions of most 64 bit operations More... git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4932 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-15 06:59:21 +0000