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2013-04-15tcg-ppc64: Improve and_i32 with constantRichard Henderson2-3/+53
Use RLWINM Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Tidy or and xor patterns.Richard Henderson1-24/+31
Handle constants in common code; we'll want to reuse that later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Allow constant first argument to subRichard Henderson1-4/+17
Using SUBFIC for 16-bit signed constants. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Improve constant add and sub ops.Richard Henderson1-44/+64
Improve constant addition -- previously we'd emit useless addi with 0. Use new constraints to force the driver to pull full 64-bit constants into a register. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Rearrange integer constant constraintsRichard Henderson1-10/+33
We'll need a zero, and Z makes more sense for that. Make sure we have a full compliment of signed and unsigned 16 and 32-bit tests. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Cleanup tcg_out_moviRichard Henderson1-24/+17
The test for using movi32 was sub-optimal for TCG_TYPE_I32, comparing a signed 32-bit quantity against an unsigned 32-bit quantity. When possible, use addi+oris for 32-bit unsigned constants. Otherwise, standardize on addi+oris+ori instead of addis+ori+rldicl. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Fix setcond_i32Richard Henderson1-0/+6
We weren't ignoring the high 32 bits during a NE comparison. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use TAI and SAIRichard Henderson1-73/+70
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_shri64Richard Henderson1-2/+7
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_shli64Richard Henderson1-5/+8
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_ext32uRichard Henderson1-5/+10
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Introduce and use tcg_out_rlwRichard Henderson1-52/+20
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-15tcg-ppc64: Use TCGReg everywhereRichard Henderson1-15/+21
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add 64-bit multiword arithmetic operationsRichard Henderson1-0/+3
Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19janitor: add guards to headersPaolo Bonzini1-0/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell1-1/+0
GUEST_BASE support is now supported by all TCG backends, and is now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE define (set by every backend) and the error if it is unset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-10-06tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYSRichard Henderson1-1/+1
There are several cases that can be handled easier inside both translators and code generators if we have out-of-band values for conditions. It's easy enough to handle ALWAYS and NEVER in the natural way inside the tcg middle-end. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06tcg: remove obsolete jmp opAurelien Jarno1-10/+0
The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil1-6/+0
The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+2
Implemented with setcond if the target does not provide the optional opcode. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl1-28/+0
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets, remove dead code and support for !CONFIG_TCG_PASS_AREG0 case. Remove dyngen-exec.h and all references to it. Although included by hw/spapr_hcall.c, it does not seem to use it. Remove unused HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-06-24TCG: Fix compile breakage in tcg_dump_opsAlexander Graf1-1/+1
Commit eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convert all users (notably missing the ppc ones) to it. Fix them to the new syntax. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: malc <av1474@comtv.ru>
2012-05-15tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0Andreas Färber1-20/+12
In qemu_ld/st load the registers for the helper calls directly rather than rotating them around afterwards for AREG0. Also clobber the additional register. Signed-off-by: Andreas F?rber <afaerber@suse.de> Signed-off-by: malc <av1474@comtv.ru>
2012-05-15tcg/ppc64: Don't hardcode register numbers for qemu_ld/stAndreas Färber1-7/+9
Facilitates using r3 for prepended AREG0. Signed-off-by: Andreas F?rber <afaerber@suse.de> Signed-off-by: malc <av1474@comtv.ru>
2012-05-03Restore consistent formattingmalc1-18/+18
Signed-off-by: malc <av1474@comtv.ru>
2012-03-29qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defsLi Zhang1-1/+0
There two entries of INDEX_op_ld_i64 in the ppc_op_defs. That causes an assertion failure in tcg_add_target_add_op_defs() when --enable-debug is used on a ppc64 backend (that's ppc64 host, not target). Signed-off-by: Li Zhang <zhlcindy@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: malc <av1474@comtv.ru>
2012-03-18softmmu templates: optionally pass CPUState to memory access functionsBlue Swirl1-0/+44
Optionally, make memory access helpers take a parameter for CPUState instead of relying on global env. On most targets, perform simple moves to reorder registers. On i386, switch from regparm(3) calling convention to standard stack-based version. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-2/+2
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2011-11-19Merge branch 's390-1.0' of git://repo.or.cz/qemu/agrafBlue Swirl2-6/+6
* 's390-1.0' of git://repo.or.cz/qemu/agraf: s390x: initialize virtio dev region tcg: Use TCGReg for standard tcg-target entry points. tcg: Standardize on TCGReg as the enum for hard registers s390x: Add shutdown for TCG s390-virtio machine s390: Fix cpu shutdown for KVM s390: fix short kernel command lines s390: fix reset hypercall to reset the status s390x: implement SIGP restart and shutdown s390x: implement rrbe instruction properly s390x: update R and C bits in storage key s390x: make ipte 31-bit aware s390x: add ldeb instruction
2011-11-14tcg: Use TCGReg for standard tcg-target entry points.Richard Henderson1-4/+4
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-14tcg: Standardize on TCGReg as the enum for hard registersRichard Henderson1-2/+2
Most targets did not name the enum; tci used TCGRegister. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-11tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6David Gibson1-6/+8
tcg/ppc64/tcg-target.c has a couple of places where variables are set unconditionally, but otherwise used only for softmmu builds, not userspace only builds. This causes compiler warnings (which are fatal by default) when compiling for a ppc64 host with gcc 4.6. This patch fixes the problem by moving the code which defines and sets the variables into the CONFIG_SOFTMMU guarded regions. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil1-1/+0
It is now declared for all tcg targets in tcg.h, so the tcg target specific declarations are redundant. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17tcg/ppc64: Only one call output register needed for 64 bit hostsStefan Weil1-1/+1
The second register is only needed for 32 bit hosts. Cc: Vassili Karpov <av1474@comtv.ru> Fine-with-me'd-by: Vassili Karpov <av1474@comtv.ru> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-09tcg/ppc64: Fix zero extension code generation bug for ppc64 hostThomas Huth1-1/+1
The ppc64 code generation backend uses an rldicr (Rotate Left Double Immediate and Clear Right) instruction to implement zero extension of a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However this is wrong - this instruction clears specified low bits of the value, instead of high bits as we require for a zero extension. It should instead use an rldicl (Rotate Left Double Immediate and Clear Left) instruction. Presumably amongst other things, this causes the SLOF firmware image used with -M pseries to not boot on a ppc64 host. It appears this bug was exposed by commit 0bf1dbdcc935dfc220a93cd990e947e90706aec6 (tcg/ppc64: fix 16/32 mixup) which enabled the use of the op_ext32u_i64 operation on the ppc64 backend. Signed-off-by: Thomas Huth <thuth@de.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: malc <av1474@comtv.ru>
2011-08-22tcg/ppc64: fix 16/32 mixupmalc1-2/+2
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22tcg/ppc64: implement not_i32/64 and ext32u_i64malc2-3/+16
Signed-off-by: malc <av1474@comtv.ru>
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson1-33/+35
By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-28TCG/PPC: use stack for TCG tempsBlue Swirl1-2/+5
Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
2011-06-28tcg/ppc64: Remove tcg_out_addimalc1-5/+0
The only user (within tcg.c) was removed Signed-off-by: malc <av1474@comtv.ru>
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl1-0/+2
Delegate TCG temp_buf setup to targets, so that they can use a stack frame later instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl1-3/+3
Make functions take a parameter for CPUState instead of relying on global env. Pass CPUState pointer to TCG prologue, which moves it to AREG0. Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue change. Revert the hacks to avoid AREG0 use on Sparc hosts. Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. Compile the file without HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-08-15TCG: Revert ppc64 tcg_out_movi32 changeAndreas Färber1-1/+1
3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG target compilation in the code path without guest base. Reverting this line fixes the build. Signed-off-by: Andreas F?rber <andreas.faerber@web.de> Cc: malc <av1474@comtv.ru> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
2010-06-29tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.Richard Henderson1-5/+4
We need not reserve the register unless we're going to use it. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: malc <av1474@comtv.ru>
2010-06-16tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson1-0/+1
Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson1-2/+2
Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson1-5/+5
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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