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2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson1-0/+2
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add tcg-be-null.hRichard Henderson1-0/+2
This is a no-op backend data implementation, for those targets that are not currently using the load/store optimization path. This is prepatory to always requiring these functions in all backends. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-20tcg-sparc: Fix parenthesis warningRichard Henderson1-1/+1
error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses] Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-09-02exec: Split softmmu_defs.hRichard Henderson1-2/+0
The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change tcg_out_ld/st offset to intptr_tRichard Henderson1-2/+2
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change relocation offsets to intptr_tRichard Henderson1-3/+3
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Allow TCG_TARGET_REG_BITS to be specified independantlyRichard Henderson1-0/+8
There are several hosts for which it would be useful to use the available 64-bit registers in a 32-bit pointer environment. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Change flush_icache_range arguments to uintptr_tRichard Henderson1-8/+4
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02tcg: Add muluh and mulsh opcodesRichard Henderson1-0/+4
Use them in places where mulu2 and muls2 are used. Optimize mulx2 with dead low part to mulxh. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Move the CIE and FDE header definitions to common codeRichard Henderson1-25/+10
These will necessarily be the same layout for all hosts. This limits the amount of boilerplate required to implement jit debug for a host. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson1-0/+2
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-03-03tcg-sparc: fix buildBlue Swirl1-1/+1
Fix build breakage by 803d805bcef4ea7b7d6ef0b4929263e1160d6b3c: make tcg_out_addsub2() always available. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add signed multiword multiplication operationsRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Add 64-bit multiword arithmetic operationsRichard Henderson1-0/+3
Matching the 32-bit multiword arithmetic that we already have. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg-sparc: Always implement 32-bit multiword opsRichard Henderson2-6/+7
Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23tcg: Make 32-bit multiword operations optional for 64-bit hostsRichard Henderson1-0/+4
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19janitor: add guards to headersPaolo Bonzini1-0/+3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-10-19Merge branch 'linux-user-for-upstream' of ↵Aurelien Jarno1-2/+0
git://git.linaro.org/people/rikuvoipio/qemu * 'linux-user-for-upstream' of git://git.linaro.org/people/rikuvoipio/qemu: linux-user: register align p{read, write}64 linux-user: ppc: mark as long long aligned tcg: Remove TCG_TARGET_HAS_GUEST_BASE define configure: Remove unnecessary host_guest_base code linux-user: If loading fails, print error as string, not number linux-user: Fix siginfo handling alpha-linux-user: Fix sigaltstack structure definition linux-user: Implement gethostname linux-user: Perform more checks on iovec lists linux-user: fix multi-threaded /proc/self/maps linux-user: fix statfs
2012-10-13tcg-sparc: Emit MOVR insns for setcond_i64 and movcond_64Richard Henderson1-5/+30
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Emit BPr insns for brcond_i64Richard Henderson1-2/+47
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Drop use of Bicc in favor of BPccRichard Henderson1-160/+145
Now that we're always sparcv9, we can not bother using Bicc for 32-bit branches and BPcc for 64-bit branches and instead always use BPcc. New interfaces allow less direct use of tcg_out32 and raw numbers inside the qemu_ld/st routines. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Optimize setcond2 equality compare with 0.Richard Henderson1-3/+12
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Use Z constraint for %g0Richard Henderson2-60/+66
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Fix add2/sub2Richard Henderson1-8/+22
We must care not to clobber the high parts before we consume them. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Fix setcondRichard Henderson1-14/+19
The set of comparisons that can immediately use the carry are LTU/GEU, not LTU/LEU. Don't swap operands when we need a temp register; the register may already be in use from setcond2. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Fix qemu_st for 32-bitRichard Henderson1-3/+4
The datalo variable is still live in the miss path. Use another when reconstructing the full data value. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Fix setcond2Richard Henderson1-20/+18
Like brcond2, use tcg_high_cond. Use movcc instead of branches. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Implement movcond.Richard Henderson2-9/+38
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-13tcg-sparc: Fix brcond2Richard Henderson1-16/+7
Much the same problem as recently fixed for hppa. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-12tcg: Remove TCG_TARGET_HAS_GUEST_BASE definePeter Maydell1-2/+0
GUEST_BASE support is now supported by all TCG backends, and is now mandatory. Drop the now-pointless TCG_TARGET_HAS_GUEST_BASE define (set by every backend) and the error if it is unset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-10-06tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYSRichard Henderson1-1/+1
There are several cases that can be handled easier inside both translators and code generators if we have out-of-band values for conditions. It's easy enough to handle ALWAYS and NEVER in the natural way inside the tcg middle-end. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06tcg: remove obsolete jmp opAurelien Jarno1-2/+0
The TCG jmp operation doesn't really make sense in the QEMU context, it is unused, it is not implemented by some targets, and it is wrongly implemented by some others. This patch simply removes it. Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Stefan Weil<sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rthBlue Swirl2-527/+476
* 'tcg-sparc' of git://repo.or.cz/qemu/rth: tcg-sparc: Preserve branch destinations during retranslation tcg-sparc: Fix and enable direct TB chaining. tcg-sparc: Add %g/%o registers to alloc_order tcg-sparc: Use defines for temporaries. tcg-sparc: Mask shift immediates to avoid illegal insns. tcg-sparc: Clean up cruft stemming from attempts to use global registers. tcg-sparc: Change AREG0 in generated code to %i0. tcg-sparc: Support GUEST_BASE. tcg-sparc: Fix qemu_ld/st to handle 32-bit host. tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode. tcg-sparc: Don't MAP_FIXED on top of the program tcg-sparc: Fix ADDX opcode. tcg-sparc: Hack in qemu_ld/st64 for 32-bit. linux-user: Use memcpy in get_user/put_user.
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil1-6/+0
The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21tcg-sparc: Preserve branch destinations during retranslationRichard Henderson1-8/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Fix and enable direct TB chaining.Richard Henderson1-3/+18
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Add %g/%o registers to alloc_orderRichard Henderson1-0/+13
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Use defines for temporaries.Richard Henderson1-56/+59
And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Mask shift immediates to avoid illegal insns.Richard Henderson1-6/+12
The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Clean up cruft stemming from attempts to use global registers.Richard Henderson2-47/+26
Don't use -ffixed-gN. Don't link statically. Don't save/restore AREG0 around calls. Don't allocate space on the stack for AREG0 save. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Change AREG0 in generated code to %i0.Richard Henderson2-8/+3
We can now move the TCG variable from %g[56] to a call-preserved windowed register. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Support GUEST_BASE.Richard Henderson2-3/+25
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Fix qemu_ld/st to handle 32-bit host.Richard Henderson1-429/+348
At the same time, split out the tlb load logic to a new function. Fixes the cases of two data registers and two address registers. Fixes the signature of, and adds missing, qemu_ld/st opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.Richard Henderson2-18/+9
Current code doesn't actually work in 32-bit mode at all. Since no one really noticed, drop the complication of v7 and v8 cpus. Eliminate the --sparc_cpu configure option and standardize macro testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Fix ADDX opcode.Richard Henderson1-1/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Hack in qemu_ld/st64 for 32-bit.Richard Henderson1-0/+3
Not actually implemented, but at least we avoid the tcg assert at startup. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg: Introduce movcondRichard Henderson1-0/+2
Implemented with setcond if the target does not provide the optional opcode. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15Remove unused CONFIG_TCG_PASS_AREG0 and dead codeBlue Swirl2-31/+0
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets, remove dead code and support for !CONFIG_TCG_PASS_AREG0 case. Remove dyngen-exec.h and all references to it. Although included by hw/spapr_hcall.c, it does not seem to use it. Remove unused HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-03-24tcg-sparc: Add debug_frame support.Richard Henderson1-0/+63
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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