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2011-10-01tcg-i386: Introduce limited deposit supportJan Kiszka4-4/+40
x86 cannot provide an optimized generic deposit implementation. But at least for a few special cases, namely for writing bits 0..7, 8..15, and 0..15, versions using only a single instruction are feasible. Introducing such limited support improves emulating 16-bit x86 code on x86, but also rarer cases where 32-bit or 64-bit code accesses bytes or words. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg/arm: Remove unused tcg_out_addi()Peter Maydell1-15/+0
Remove the unused function tcg_out_addi() from the ARM TCG backend; this fixes a compilation failure on ARM hosts with newer gcc. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg: Add some assertionsStefan Weil1-0/+2
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg: Add forward declarations for local functionsStefan Weil1-0/+16
These functions are defined in the tcg target specific file tcg-target.c. The forward declarations assert that every tcg target uses the same function prototype. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.hStefan Weil8-21/+1
It is now declared for all tcg targets in tcg.h, so the tcg target specific declarations are redundant. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01tcg: Declare TCG_TARGET_REG_BITS in tcg.hStefan Weil1-0/+10
TCG_TARGET_REG_BITS can be determined by the compiler, so there is no need to declare it for each individual tcg target. This is especially important for new tcg targets which will be supported by the tcg interpreter. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17tcg/ppc64: Only one call output register needed for 64 bit hostsStefan Weil1-1/+1
The second register is only needed for 32 bit hosts. Cc: Vassili Karpov <av1474@comtv.ru> Fine-with-me'd-by: Vassili Karpov <av1474@comtv.ru> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17tcg/sparc: Only one call output register needed for 64 bit hostsStefan Weil1-2/+4
The second register is only needed for 32 bit hosts. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17tcg/s390: Only one call output register needed for 64 bit hostsStefan Weil1-1/+3
The second register is only needed for 32 bit hosts. Cc: Alexander Graf <agraf@suse.de> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17tcg/ia64: Only one call output register needed for 64 bit hostsStefan Weil1-3/+2
The second register is never used for ia64 hosts. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17tcg/i386: Only one call output register needed for 64 bit hostsStefan Weil1-1/+3
The second register is only needed for 32 bit hosts. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-09tcg/ppc64: Fix zero extension code generation bug for ppc64 hostThomas Huth1-1/+1
The ppc64 code generation backend uses an rldicr (Rotate Left Double Immediate and Clear Right) instruction to implement zero extension of a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However this is wrong - this instruction clears specified low bits of the value, instead of high bits as we require for a zero extension. It should instead use an rldicl (Rotate Left Double Immediate and Clear Left) instruction. Presumably amongst other things, this causes the SLOF firmware image used with -M pseries to not boot on a ppc64 host. It appears this bug was exposed by commit 0bf1dbdcc935dfc220a93cd990e947e90706aec6 (tcg/ppc64: fix 16/32 mixup) which enabled the use of the op_ext32u_i64 operation on the ppc64 backend. Signed-off-by: Thomas Huth <thuth@de.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: malc <av1474@comtv.ru>
2011-09-01tcg/ppc/tcg-target.c: Avoid 'set but not used' gcc warningsPeter Maydell1-10/+10
Move the declaration and initialisation of some variables in tcg_out_qemu_ld and tcg_out_qemu_st inside CONFIG_SOFTMMU, to avoid the "variable set but not used" warning of gcc 4.6. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: malc <av1474@comtv.ru>
2011-08-28TCG: improve optimizer debuggingBlue Swirl1-6/+9
Use enum TCGOpcode instead of plain old int so that the name of current op can be seen in GDB. Add a default case to switch so that GCC does not complain about unhandled enum cases. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-23tcg: Update --enable-debug for TCG_OPF_NOT_PRESENT.Richard Henderson1-7/+8
Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-22tcg/ppc64: fix 16/32 mixupmalc1-2/+2
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22tcg/ppc64: implement not_i32/64 and ext32u_i64malc2-3/+16
Signed-off-by: malc <av1474@comtv.ru>
2011-08-22tcg/ppc32: implement deposit_i32malc2-1/+13
Signed-off-by: malc <av1474@comtv.ru>
2011-08-21tcg-ia64: Fix typos in AREG0 setup in prologue.Richard Henderson1-2/+2
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21tcg-hppa: Fix CPU_TEMP_BUF_NLONGS oversight.Richard Henderson1-1/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21tcg: Constant fold neg, andc, orc, eqv, nand, nor.Richard Henderson1-0/+27
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21tcg: Always define all of the TCGOpcode enum members.Richard Henderson14-1008/+837
By always defining these symbols, we can eliminate a lot of ifdefs. To allow this to be checked reliably, the semantics of the TCG_TARGET_HAS_* macros must be changed from def/undef to true/false. This allows even more ifdefs to be removed, converting them into C if statements. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-21tcg: Add and use TCG_OPF_64BIT.Richard Henderson4-131/+67
This allows the simplification of the op_bits function from tcg/optimize.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori1-4/+4
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-07TCG: fix copy propagationBlue Swirl2-6/+14
Copy propagation introduced in 22613af4a6d9602001e6d0e7b6d98aa40aa018dc considered only global registers. However, register temps and stack allocated locals must be handled differently because register temps don't survive across brcond. Fix by propagating only within same class of temps. Tested-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30TCG: fix breakage by previous patchBlue Swirl1-7/+12
Fix incorrect logic and typos in previous commit 1bfd07bdfe56cea43dbe258dcb161e46b0ee29b7. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30TCG: fix breakage on some RISC hostsBlue Swirl1-13/+115
Fix breakage by a640f03178c22355a158fa9378e4f8bfa4f517a6 and 55c0975c5b358e948b9ae7bd7b07eff92508e756. Some TCG targets don't implement all TCG ops, so make optimizing those conditional. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30Do constant folding for unary operations.Kirill Batuzov1-0/+59
Perform constant folding for NOT and EXT{8,16,32}{S,U} operations. Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30Do constant folding for shift operations.Kirill Batuzov1-0/+72
Perform constant forlding for SHR, SHL, SAR, ROTR, ROTL operations. Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30Do constant folding for boolean operations.Kirill Batuzov1-0/+37
Perform constant folding for AND, OR, XOR operations. Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30Do constant folding for basic arithmetic operations.Kirill Batuzov1-0/+125
Perform actual constant folding for ADD, SUB and MUL operations. Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30Add copy and constant propagation.Kirill Batuzov1-2/+180
Make tcg_constant_folding do copy and constant propagation. It is a preparational work before actual constant folding. Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30Add TCG optimizations stubKirill Batuzov3-0/+106
Added file tcg/optimize.c to hold TCG optimizations. Function tcg_optimize is called from tcg_gen_code_common. It calls other functions performing specific optimizations. Stub for constant folding was added. Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20tcg/mips: Fix regression caused by typo (copy + paste bug)Stefan Weil1-1/+1
cppcheck reports an error: qemu/tcg/mips/tcg-target.c:1487: error: Invalid number of character (() The unpatched code won't compile on mips hosts starting with commit cea5f9a28faa528b6b1b117c9ab2d8828f473fef. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-16tcg/README: Expand advice on number of TCG ops per target insnPeter Maydell1-1/+9
Expand the note on the number of TCG ops generated per target insn, to be clearer about the range of applicability of the 20 op rule of thumb. Also add a note about the hard MAX_OP_PER_INSTR limit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-02TCG/PPC: use stack for TCG tempsBlue Swirl2-4/+10
Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01tcg-hppa: Support deposit opcode.Richard Henderson2-4/+21
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01TCG/HPPA: use stack for TCG tempsBlue Swirl1-2/+7
Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-01TCG/HPPA: use TCG_REG_CALL_STACK instead of TCG_REG_SPBlue Swirl1-14/+16
Use TCG_REG_CALL_STACK instead of TCG_REG_SP for consistency. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-28tcg/ppc64: Remove tcg_out_addimalc1-5/+0
The only user (within tcg.c) was removed Signed-off-by: malc <av1474@comtv.ru>
2011-06-28tcg/ppc: Remove tcg_out_addimalc1-5/+0
The only user (within tcg.c) was removed Signed-off-by: malc <av1474@comtv.ru>
2011-06-26TCG/Sparc64: use stack for TCG tempsBlue Swirl2-3/+6
Use stack instead of temp_buf array in CPUState for TCG temps. On Sparc64, stack pointer is not aligned but there is a fixed bias of 2047, so don't try to enforce alignment. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG/x86: use stack for TCG tempsBlue Swirl1-10/+12
Use stack instead of temp_buf array in CPUState for TCG temps. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG/x86: use TCG_REG_CALL_STACK instead of TCG_REG_ESPBlue Swirl1-4/+4
Except for specific cases where the use of %esp changes the encoding of the instruction, it's cleaner to use TCG_REG_CALL_STACK instead of TCG_REG_ESP. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG: remove broken stack allocation for call argumentsBlue Swirl1-6/+3
The code for stack allocation for call arguments is way too simplistic to actually work on targets with non-trivial stack allocation policies, e.g. ppc64. We've also already allocated TCG_STATIC_CALL_ARGS_SIZE worth of stack for calls which should be well more than any helper needs. Remove broken dynamic stack allocation code and replace it with an assert. Should dynamic stack allocation ever be needed again, target specific functions should be added. Thanks to Richard Henderson for the analysis. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26TCG: fix negative frame offset calculationsBlue Swirl1-3/+7
size_t is unsigned, so the frame offset calculations can be incorrect for negative offsets. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl9-0/+18
Delegate TCG temp_buf setup to targets, so that they can use a stack frame later instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl10-32/+40
Make functions take a parameter for CPUState instead of relying on global env. Pass CPUState pointer to TCG prologue, which moves it to AREG0. Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue change. Revert the hacks to avoid AREG0 use on Sparc hosts. Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. Compile the file without HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+0
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-03tcg: Fix unused-but-set-variable warningChristophe Fergeau1-2/+2
Based on a patch from Hans de Goede <hdegoede@redhat.com> This warning is new in gcc 4.6. Acked-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Christophe Fergeau <cfergeau@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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