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2014-02-08tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTRPeter Maydell1-0/+3
We have macros for marking TCGv values as unused, checking if they are unused and comparing them to each other. However these only exist for TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-01tcg/s390: Remove sigill_handlerRichard Henderson1-19/+0
Commit c9baa30f42a87f61627391698f63fa4d1566d9d8 failed to delete all of the relevant code, leading to Werrors about unused symbols. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-01-30Merge remote-tracking branch 'rth/tcg-movbe' into stagingPeter Maydell1-48/+97
* rth/tcg-movbe: tcg/i386: cleanup useless #ifdef tcg/i386: use movbe instruction in qemu_ldst routines tcg/i386: add support for three-byte opcodes tcg/i386: remove hardcoded P_REXW value disas/i386.c: disassemble movbe instruction Message-id: 1390692772-15282-1-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-30TCG: Fix I64-on-32bit-host temporariesAlexander Graf1-1/+1
We have cache pools of temporaries that we can reuse later when they've already been allocated before. These cache pools differenciate between the target TCG variable type they contain. So we have one pool for I32 and one pool for I64 variables. On a 32bit system, we can't work with 64bit registers though. So instead we spawn two I32 temporaries for every I64 temporary we create. All caching works the same way as on a real 64-bit system though: We create a cache entry in the 64bit array for the first i32 index. However, when we free such a temporary we free it to the pool of its type (which is always i32 on 32bit systems) rather than its base_type (which is i64 or i32 depending on the variable). This means we put a temporary that is of base_type == i64 into the i32 preallocated temporary pool. Eventually, this results in failures like this on 32bit hosts: qemu-system-ppc64: tcg/tcg.c:515: tcg_temp_new_internal: Assertion `ts->base_type == type' failed. This patch makes the free routine use the base_type instead for the free case, so it's consistent with the temporary allocation. It fixes the above failure for me. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1390146811-59936-1-git-send-email-agraf@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-25tcg/i386: cleanup useless #ifdefAurelien Jarno1-2/+0
TCG_TARGET_HAS_movcond_i32 is always defined to 1 in tcg-target.h, so remove the corresponding #ifdef #endif sequence, left from a previous refactoring. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-25tcg/i386: use movbe instruction in qemu_ldst routinesAurelien Jarno1-37/+80
The movbe instruction has been added on some Intel Atom CPUs and on recent Intel Haswell CPUs. It allows to load/store a value and at the same time bswap it. This patch detects the avaibility of this instruction and when available use it in the qemu load/store routines in replacement of load/store + bswap. Note that for 16-bit unsigned loads, movbe + movzw is basically the same as movzw + bswap, so the patch doesn't touch this case. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [RTH: Reduced the number of conditionals using "movop".] Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-25tcg/i386: add support for three-byte opcodesAurelien Jarno1-8/+16
Add support for three-byte opcodes, starting with the 0x0f 0x38 prefix. Use P_EXT38 as the new constant, and shift all other constants so that P_EXT and P_EXT38 have neighbouring values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [RTH: Changed the name from P_EXT2 to P_EXT38.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-01-25tcg/i386: remove hardcoded P_REXW valueAurelien Jarno1-1/+1
P_REXW is defined has a constant at the beginning of i386/tcg-target.c, but the corresponding bit is later used in a harcoded way, which defeat the purpose of a constant. Fix that by using a conditional expression operator instead of a shift. On x86 this actually makes the code slightly smaller as GCC does in practice (opc >> 8) & 8 instead of (opc & 0x800) >> 8 so the constants are smaller to load. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-12-21tcg/i386: fix a commentAurelien Jarno1-1/+1
The comments apply to 8-bit stores, not 8-byte stores. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-10tcg: Use bitmaps for free temporariesRichard Henderson2-22/+21
We previously allocated 32-bits per temp for the next_free_temp entry. We now allocate 4 bits per temp across the 4 bitmaps. Using a linked list meant that if a translator is tweeked, resulting in temps being freed in a different order, that would have follow-on effects throughout the TB. Always allocating the lowest free temp means that follow-on effects are minimized, which can make it easier to diff output when debugging the translators. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-30tcg-s390: Use qemu_getauxval in query_facilitiesRichard Henderson1-83/+12
No need to set up a SIGILL signal handler for detection anymore. Remove a ton of sanity checks that must be true, given that we're requiring a 64-bit build (the note about 31-bit KVM is satisfied by configuring with TCI). Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-30tcg-arm: Use qemu_getauxvalRichard Henderson1-9/+5
Allow host detection on linux systems without glibc 2.16 or later. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-30tcg-ppc64: Use qemu_getauxvalRichard Henderson1-9/+2
Allow host detection on linux systems without glibc 2.16 or later. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Introduce tcg_opc_bswap64_iRichard Henderson1-35/+28
Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Introduce tcg_opc_ext_iRichard Henderson1-30/+24
Being able to "extend" from 64-bits (with a mov) simplifies a few places where the conditional breaks the train of thought. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Introduce tcg_opc_movi_aRichard Henderson1-16/+16
Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Introduce tcg_opc_mov_aRichard Henderson1-19/+16
Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Use A3 form of logical operationsRichard Henderson1-30/+34
We can and/or/xor/andcm small constants, saving one cycle. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Use SUB_A3 and ADDS_A4 for subtractionRichard Henderson1-2/+23
We can subtract from more small constants that just 0 with one insn, and we can add the negative for most small constants. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Use ADDS for small additionRichard Henderson1-4/+16
Avoids a wasted cycle loading up small constants. Simplify the code assuming the tcg optimizer is going to work and don't expect the first operand of the add to be constant. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Avoid unnecessary stop bit in tcg_out_aluRichard Henderson1-11/+6
When performing an operation with two input registers, we'd leave the stop bit (and thus an extra cycle) that's only needed when one or the other input is a constant. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Move AREG0 to R32Richard Henderson2-9/+8
Since the move away from the global areg0, we're no longer globally reserving areg0. Which means our use of R7 clobbers a call-saved register. Shift areg0 into the windowed registers. Indeed, choose the incoming parameter register that it comes to us by. This requires moving the register holding the return address elsewhere. Choose R33 for tidiness. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Simplify brcondRichard Henderson1-34/+10
There was a misconception that a stop bit is required between a compare and the branch that uses the predicate set by the compare. This lead to the usage of an extra bundle in which to perform the compare. The extra bundle left room for constants to be loaded for use with the compare insn. If we pack the compare and the branch together in the same bundle, then there's no longer any room for non-zero constants. At which point we can eliminate half the function by not handling them. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Handle constant callsRichard Henderson1-3/+35
Using only indirect calls results in 3 bundles (one to load the descriptor address), and 4 stop bits. By looking through the descriptor to the constants, we can perform the call with 2 bundles and only 1 stop bit. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Use shortcuts for nop insnsRichard Henderson1-124/+127
There's no need to go through the full opcode-to-insn function call to generate nops. This makes the source a bit more readable. Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-11-18tcg-ia64: Use TCGMemOp within qemu_ldst routinesRichard Henderson1-82/+91
Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc64: Support new ldst opcodesRichard Henderson2-62/+17
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc: Support new ldst opcodesRichard Henderson2-66/+33
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc64: Convert to le/be ldst helpersRichard Henderson1-16/+22
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc: Convert to le/be ldst helpersRichard Henderson1-24/+33
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc64: Use TCGMemOp within qemu_ldst routinesRichard Henderson1-39/+45
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-ppc: Use TCGMemOp within qemu_ldst routinesRichard Henderson1-56/+48
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Improve GUEST_BASE qemu_ld/stRichard Henderson1-104/+116
If we pull the code to emit the actual load/store into a subroutine, we can share the reg+reg addressing mode code between softmmu and usermode. This lets us load GUEST_BASE into a temporary register rather than attempting to add it piece-wise to the address. Which lets us use movw+movt for armv7, rather than (up to) 4 adds. Code size for pre-armv7 stays the same. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Convert to new ldst opcodesRichard Henderson2-71/+38
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Tidy variable naming convention in qemu_ld/stRichard Henderson1-115/+115
s/addr_reg2/addrhi/ s/addr_reg/addrlo/ s/data_reg2/datahi/ s/data_reg/datalo/ Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Convert to le/be ldst helpersRichard Henderson1-21/+29
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-arm: Use TCGMemOp within qemu_ldst routinesRichard Henderson1-64/+61
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-i386: Support new ldst opcodesRichard Henderson2-90/+51
No support for helpers with non-default endianness yet, but good enough to test the opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-i386: Remove "cb" output restriction from qemu_st8 for i386Richard Henderson1-2/+8
Once we form a combined qemu_st_i32 opcode, we won't be able to have separate constraints based on size. This one is fairly easy to work around, since eax is available as a scratch register. When storing variable data, this tends to merely exchange one mov for another. E.g. -: mov %esi,%ecx ... -: mov %cl,(%edx) +: mov %esi,%eax +: mov %al,(%edx) Where we do have a regression is when storing constant data, in which we may load the constant into edi, when only ecx/ebx ought to be used. The proper way to recover this regression is to allow constants as arguments to qemu_st_i32, so that we never load the constant data into a register at all, must less the wrong register. TBD. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-i386: Tidy softmmu routinesRichard Henderson1-249/+208
Pass two TCGReg to tcg_out_tlb_load, rather than idx+args. Move ldst_optimization routines just below tcg_out_tlb_load to avoid the need for forward declarations. Use TCGReg enum in preference to int where apprpriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg-i386: Use TCGMemOp within qemu_ldst routinesRichard Henderson1-64/+59
Step one in the transition, with constants passed down from tcg_out_op. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-12tcg: Use TCGMemOp for TCGLabelQemuLdst.opcRichard Henderson1-1/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10exec: Add both big- and little-endian memory helpersRichard Henderson1-16/+53
Step three in the transition: helpers not tied to the target "default" endianness. To be used when the guest uses a memory operation with non-default endianness. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add qemu_ld_st_i32/64Richard Henderson14-239/+368
Step two in the transition, adding the new ldst opcodes. Keep the old opcodes around until all backends support the new opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add TCGMemOpRichard Henderson1-0/+54
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add tcg-be-ldst.hRichard Henderson8-158/+112
Move TCGLabelQemuLdst and related stuff out of tcg.h. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add tcg-be-null.hRichard Henderson6-0/+53
This is a no-op backend data implementation, for those targets that are not currently using the load/store optimization path. This is prepatory to always requiring these functions in all backends. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg-aarch64: Update to helper_ret_*_mmu routinesRichard Henderson1-12/+16
A minimal update to use the new helpers with the return address argument. Tested-by: Claudio Fontana <claudio.fontana@linaro.org> Reviewed-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Merge tcg_register_helper into tcg_context_initRichard Henderson2-16/+6
Eliminates the repeated checks for having created the s->helpers hash table. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Add tcg-runtime.c helpers to all_helpersRichard Henderson1-0/+16
For the few targets that actually use these, we'd not report them symbolicly in the tcg opcode logs. Signed-off-by: Richard Henderson <rth@twiddle.net>
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