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2013-12-02misc: Use new rotate functionsStefan Weil1-8/+4
Signed-off-by: Stefan Weil <sw@weilnetz.de> (cherry picked from commit 3df2b8fde949be86d8a78923c992fdd698d4ea4c) Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
2013-12-02tci: Add implementation of rotl_i64, rotr_i64Stefan Weil1-1/+0
It is used by qemu-ppc64 when running Debian's busybox-static. Cc: qemu-stable <qemu-stable@nongnu.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <rth@twiddle.net> (cherry picked from commit d285bf784b6234e994ce73c05c82c9fb6429df00) Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
2013-08-08tcg/mips: fix invalid op definition errorsJames Hogan1-0/+10
tcg/mips/tcg-target.h defines various operations conditionally depending upon the isa revision, however these operations are included in mips_op_defs[] unconditionally resulting in the following runtime errors if CONFIG_DEBUG_TCG is defined: Invalid op definition for movcond_i32 Invalid op definition for rotl_i32 Invalid op definition for rotr_i32 Invalid op definition for deposit_i32 Invalid op definition for bswap16_i32 Invalid op definition for bswap32_i32 tcg/tcg.c:1196: tcg fatal error Fix with ifdefs like the i386 backend does for movcond_i32. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-30tci: Fix broken build (compiler warning caused by redefined macro BIT)Stefan Weil1-3/+0
The definition of macro BIT in tci/tcg-target.c now conflicts with the definition of the same macro in includes qemu/bitops.h. This conflict was triggered by a recent change in the include chain of tcg.c (probably commit 949fc82314cc84162e64a5323764527a542421ce). Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1375216883-23969-1-git-send-email-sw@weilnetz.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-nextRichard Henderson1-53/+203
2013-07-15tcg/aarch64: Implement tlb lookup fast pathJani Kokkonen1-50/+174
Supports CONFIG_QEMU_LDST_OPTIMIZATION Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
2013-07-09tcg-arm: Implement tcg_register_jitRichard Henderson1-9/+67
Allows unwinding past the code_gen_buffer. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame sizeRichard Henderson1-3/+3
We can check the condition at compile time, rather than run time. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Move the CIE and FDE header definitions to common codeRichard Henderson4-76/+51
These will necessarily be the same layout for all hosts. This limits the amount of boilerplate required to implement jit debug for a host. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Fix high_pc fields in .debug_infoRichard Henderson1-2/+2
I don't think the debugger actually looks at this for anything, using the correct .debug_frame contents, but might as well get it all correct. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Use AT_PLATFORM to detect the host ISARichard Henderson1-4/+16
With this we can generate armv7 insns even when the OS compiles for a lower common denominator. The macros are arranged so that when we do compile for a given ISA, all of the runtime checks for that ISA are optimized away. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Simplify logic in detecting the ARM ISA in useRichard Henderson1-39/+23
GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which will make us nicely forward compatible with ARMv8 AArch32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Rename use_armv5_instructions to use_armvt5_instructionsRichard Henderson1-6/+6
As it really controls the availability of a thumb interworking instruction on armv5t. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Make use of conditional availability of opcodes for divideRichard Henderson2-8/+22
We can now detect and use divide instructions at runtime, rather than having to restrict their availability to compile-time. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Simplify logic using TCG_OPF_NOT_PRESENTRichard Henderson3-15/+18
Expand the definition of "not present" to include "should not be present". This means we can simplify the logic surrounding the generic tcg opcodes for which the host backend ought not be providing definitions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Allow non-constant control macrosRichard Henderson1-1/+1
This allows TCG_TARGET_HAS_* to be a variable rather than a constant, which allows easier support for differing ISA levels for the host. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-ppc64: Don't implement remRichard Henderson2-28/+2
Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-ppc: Don't implement remRichard Henderson2-15/+1
Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg-arm: Don't implement remRichard Henderson2-16/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-09tcg: Split rem requirement from div requirementRichard Henderson12-12/+50
There are several hosts with only a "div" insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-07-03tcg/aarch64: implement ldst 12bit scaled uimm offsetClaudio Fontana1-3/+29
implement the 12bit scaled unsigned immediate offset variant of LDR/STR. This improves code size by avoiding the movi + ldst_r for naturally aligned offsets in range. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: rotr_i32 rotates wrong amountAnton Blanchard1-1/+1
rotr_i32 calculates the amount to left shift and puts it into a temporary, but then doesn't use it when doing the shift. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: Fix add2_i64Anton Blanchard1-7/+7
add2_i64 was adding the lower double word to the upper double word of each input. Fix this so we add the lower double words, then the upper double words with carry propagation. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: bswap64 rotates output 32 bitsAnton Blanchard1-2/+0
If our input and output is in the same register, bswap64 tries to undo a rotate of the input. This just ends up rotating the output. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-17tcg-ppc64: Fix RLDCL opcodeAnton Blanchard1-5/+6
The rldcl instruction doesn't have an sh field, so the minor opcode is shifted 1 bit. We were using the XO30 macro which shifted the minor opcode 2 bits. Remove XO30 and add MD30 and MDS30 macros which match the Power ISA categories. Cc: qemu-stable@nongnu.org Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-06-14Merge remote-tracking branch 'pmaydell/tcg-aarch64.next' into stagingAnthony Liguori2-0/+1503
# By Claudio Fontana (9) and others # Via Peter Maydell * pmaydell/tcg-aarch64.next: MAINTAINERS: add tcg/aarch64 maintainer configure: permit compilation on arm aarch64 tcg/aarch64: implement user mode qemu ld/st user-exec.c: aarch64 initial implementation of cpu_signal_handler tcg/aarch64: implement sign/zero extend operations tcg/aarch64: implement byte swap operations tcg/aarch64: implement AND/TEST immediate pattern tcg/aarch64: improve arith shifted regs operations tcg/aarch64: implement new TCG target for aarch64 include/elf.h: add aarch64 ELF machine and relocs configure: Drop CONFIG_ATFILE test linux-user: Drop direct use of openat etc syscalls linux-user: Allow getdents to be provided by getdents64 Message-id: 1371052645-9006-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-06-12tcg/aarch64: implement user mode qemu ld/stJani Kokkonen1-5/+116
also put aarch64 in the list of archs that do not need an ldscript. Signed-off-by: Jani Kokkoken <jani.kokkonen@huawei.com> Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 51AF40EE.1000104@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-12tcg/aarch64: implement sign/zero extend operationsClaudio Fontana2-12/+66
implement the optional sign/zero extend operations with the dedicated aarch64 instructions. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 51AC9A58.40502@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-12tcg/aarch64: implement byte swap operationsClaudio Fontana2-5/+37
implement the optional byte swap operations with the dedicated aarch64 instructions. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 51AC9A33.9050003@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-12tcg/aarch64: implement AND/TEST immediate patternClaudio Fontana1-0/+34
add functions to AND/TEST registers with immediate patterns. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 51AC9A0C.3090303@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-12tcg/aarch64: improve arith shifted regs operationsClaudio Fontana1-18/+30
for arith operations, add SUBS, ANDS, ADDS and add a shift parameter so that all arith instructions can make use of shifted registers. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 51AC998B.7070506@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-12tcg/aarch64: implement new TCG target for aarch64Claudio Fontana2-0/+1260
add preliminary support for TCG target aarch64. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 51A5C596.3090108@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-05tcg: Remove redundant tcg_target_init checksRichard Henderson3-19/+0
We've got a compile-time check for the condition in exec/cpu-defs.h. Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: liguang <lig.fnst@cn.fujitsu.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-05-09tcg/optimize: fix setcond2 optimizationAurelien Jarno1-0/+1
When setcond2 is rewritten into setcond, the state of the destination temp should be reset, so that a copy of the previous value is not used instead of the result. Reported-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-03tcg-arm: Use movi32 in exit_tbRichard Henderson1-9/+7
Avoid the mini constant pool for armv7, and avoid replicating the test for pre-v7. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-03tcg-arm: Fix 64-bit tlb load for pre-v6Richard Henderson1-1/+1
Found by inspection, since the effect of the bug was simply to send all memory ops through the slow path. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-27tcg-arm: Remove long jump from tcg_out_goto_labelRichard Henderson1-6/+1
Branches within a TB will always be within 16MB. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATIONRichard Henderson1-107/+202
Move the slow path out of line, as the TODO's mention. This allows the fast path to be unconditional, which can speed up the fast path as well, depending on the core. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use movi32 + blx for calls on v7Richard Henderson1-0/+3
Work better with branch predition when we have movw+movt, as the size of the code is the same. Perhaps re-evaluate when we have a proper constant pool. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Delete the 'S' constraintRichard Henderson1-4/+2
After the previous patch, 's' and 'S' are the same. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Improve scheduling of tcg_out_tlb_readRichard Henderson1-53/+57
The schedule was fully serial, with no possibility for dual issue. The old schedule had a minimal issue of 7 cycles; the new schedule has a minimal issue of 5 cycles. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Split out tcg_out_tlb_readRichard Henderson1-99/+70
Share code between qemu_ld and qemu_st to process the tlb. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Cleanup most primitive load store subroutinesRichard Henderson1-124/+111
Use even more primitive helper functions to avoid lots of duplicated code. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Cleanup multiply subroutinesRichard Henderson1-40/+45
Make the code more readable by only having one copy of the magic numbers, swapping registers as needed prior to that. Speed the compiler by not applying the rd == rn avoidance for v6 or later. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use R12 for the tcg temporaryRichard Henderson1-1/+1
R12 is call clobbered, while R8 is call saved. This change gives tcg one more call saved register for real data. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Use TCG_REG_TMP name for the tcg temporaryRichard Henderson1-58/+60
Don't hard-code R8. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Implement division instructionsRichard Henderson2-1/+42
An armv7 extension implements division, present on Cortex A15. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Implement deposit for armv7Richard Henderson2-4/+42
We have BFI and BFC available for implementing it. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Improve constant generationRichard Henderson1-23/+44
Try fully rotated arguments to mov and mvn before trying movt or full decomposition. Begin decomposition with mvn when it looks like it'll help. Examples include -: mov r9, #0x00000fa0 -: orr r9, r9, #0x000ee000 -: orr r9, r9, #0x0ff00000 -: orr r9, r9, #0xf0000000 +: mvn r9, #0x0000005f +: eor r9, r9, #0x00011000 Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-04-27tcg-arm: Handle constant arguments to add2/sub2Richard Henderson1-48/+58
We get to re-use the _rIN and _rIK subroutines to handle the various combinations of add vs sub. Fold the << 21 into the opcode enum values so that we can explicitly add TO_CPSR as desired. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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