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2017-09-17tcg/mips: Fully convert tcg_target_op_defRichard Henderson1-154/+170
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg/sparc: Fully convert tcg_target_op_defRichard Henderson1-102/+137
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg/ppc: Fully convert tcg_target_op_defRichard Henderson1-153/+168
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg/arm: Fully convert tcg_target_op_defRichard Henderson1-79/+107
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg/aarch64: Fully convert tcg_target_op_defRichard Henderson1-131/+151
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg: Fix types in tcg_regset_{set,reset}_regRichard Henderson1-3/+3
There was a potential problem here with an ILP32 host with 64 host registers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg: Remove tcg_regset_set32Richard Henderson8-103/+90
It's not even clear what the interface REG and VAL32 were supposed to mean. All uses had REG = 0 and VAL32 was the bitset assigned to the destination. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg: Remove tcg_regset_{or,and,andnot,not}Richard Henderson2-5/+1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg: Remove tcg_regset_setRichard Henderson3-28/+28
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg: Remove tcg_regset_clearRichard Henderson10-16/+14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg: Add tcg_op_supportedRichard Henderson2-3/+226
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17accel/tcg: move tcg-runtime to accel/tcg/Philippe Mathieu-Daudé2-370/+0
Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170911213328.9701-4-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-17tcg/ppc: disable atomic write check on ppc32Philippe Mathieu-Daudé1-1/+3
This fixes building for ppc64 on ppc32 (changed in 5964fca8a12c): tcg/ppc/tcg-target.inc.c: In function 'tb_target_set_jmp_target': include/qemu/compiler.h:86:30: error: static assertion failed: \ "not expecting: sizeof(*(uint64_t *)jmp_addr) > ATOMIC_REG_SIZE" QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \ ^ tcg/ppc/tcg-target.inc.c:1377:9: note: in expansion of macro 'atomic_set' atomic_set((uint64_t *)jmp_addr, pair); ^ Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170911204936.5020-1-f4bug@amsat.org> [rth: Added commentary requested by pmm.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-11tcg/tci: do not use ldst label (never implemented)Philippe Mathieu-Daudé1-4/+0
changed in 659ef5cbb893, this fixes building with --enable-tcg-interpreter: /home/travis/build/qemu/qemu/tcg/tcg.c:116:14: error: ‘tcg_out_ldst_finalize’ used but never defined [-Werror] static bool tcg_out_ldst_finalize(TCGContext *s); ^ Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20170911022839.23231-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07tcg/ppc: Use constant pool for moviRichard Henderson2-4/+31
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/ppc: Look for shifted constantsRichard Henderson1-10/+48
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/ppc: Change TCG_REG_RA to TCG_REG_TBRichard Henderson1-151/+122
At this point the conversion is a wash. Loading of TB+ofs is smaller, but the actual return address from exit_tb is larger. There are a few more insns required to transition between TBs. But the expectation is that accesses to the constant pool will on the whole be smaller. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/arm: Use constant pool for callRichard Henderson1-6/+3
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/arm: Use constant pool for moviRichard Henderson2-18/+75
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/arm: Extract INSN_NOPRichard Henderson1-10/+11
We'll want this for tcg_out_nop_fill. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/arm: Code rearrangementRichard Henderson1-258/+257
Move constants before all of the functions. Move tcg_out_<format> functions before all of the others. No functional change. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/arm: Tighten tlb indexing offset testRichard Henderson1-1/+3
We are not going to use ldrd for loading the comparator for 32-bit guests, so don't limit cmp_off to 8 bits then. This eliminates one insn in the tlb load for some guests. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/arm: Improve tlb load for armv7Richard Henderson1-20/+52
Use UBFX to avoid limitation on CPU_TLB_BITS. Since we're dropping the initial shift, we need to replace the page masking. We can use MOVW+BIC to do this without shifting. The result is the same size as the armv6 path with one less conditional instruction. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/sparc: Use constant pool for moviRichard Henderson2-21/+58
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/sparc: Introduce TCG_REG_TBRichard Henderson1-30/+140
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/aarch64: Use constant pool for moviRichard Henderson2-30/+33
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/s390: Use constant pool for cmpiRichard Henderson1-69/+67
Also use CHI/CGHI for 16-bit signed constants. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/s390: Use constant pool for xoriRichard Henderson1-37/+40
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/s390: Use constant pool for oriRichard Henderson1-40/+34
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/s390: Use constant pool for andiRichard Henderson1-6/+14
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/s390: Use constant pool for moviRichard Henderson2-53/+78
Split out maybe_out_small_movi for use with other operations that want to add to the constant pool. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/s390: Fix sign of patch_reloc addendRichard Henderson1-12/+13
We were passing in -2 instead of +2, but then ignoring the actual contents of addend in the calculation. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/s390: Introduce TCG_REG_TBRichard Henderson2-12/+61
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/i386: Store out-of-range call targets in constant poolRichard Henderson2-3/+16
Already it saves 2 bytes per call, but also the constant pool entry may well be shared across multiple calls. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg: Infrastructure for managing constant poolsRichard Henderson3-0/+98
A new shared header tcg-pool.inc.c adds new_pool_label, for registering a tcg_target_ulong to be emitted after the generated code, plus relocation data to install a pointer to the data. A new pointer is added to the TCGContext, so that we dump the constant pool as data, not code. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg: Rearrange ldst label trackingRichard Henderson19-91/+57
Dispense with TCGBackendData, as it has never been used for more than holding a single pointer. Use a define in the cpu/tcg-target.h to signal requirement for TCGLabelQemuLdst, so that we can drop the no-op tcg-be-null.h stubs. Rename tcg-be-ldst.h to tcg-ldst.inc.c. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.hRichard Henderson13-17/+61
Replace the USE_DIRECT_JUMP ifdef with a TCG_TARGET_HAS_direct_jump boolean test. Replace the tb_set_jmp_target1 ifdef with an unconditional function tb_target_set_jmp_target. While we're touching all backends, add a parameter for tb->tc_ptr; we're going to need it shortly for some backends. Move tb_set_jmp_target and tb_add_jump from exec-all.h to cpu-exec.c. This opens the possibility for TCG_TARGET_HAS_direct_jump to be a runtime decision -- based on host cpu capabilities, the size of code_gen_buffer, or a future debugging switch. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-07tcg/tci: Add TCG_TARGET_DEFAULT_MORichard Henderson1-0/+5
Missed being added as part of 71650df7b0ee. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-06tcg/s390: Use slbgr for setcond le and leuRichard Henderson1-76/+43
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Use load-on-condition-2 facilityRichard Henderson2-17/+63
This allows LOAD HALFWORD IMMEDIATE ON CONDITION, eliminating one insn in some common cases. Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Use distinct-operands facilityRichard Henderson2-28/+91
This allows using a 3-operand insn form for some arithmetic, logicals and shifts. Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge ori+xori facilities check to tcg_target_op_defRichard Henderson1-68/+33
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge add2i facilities check to tcg_target_op_defRichard Henderson1-24/+14
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge muli facilities check to tcg_target_op_defRichard Henderson1-20/+25
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Merge cmpi facilities check to tcg_target_op_defRichard Henderson1-38/+30
Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-06tcg/s390: Fully convert tcg_target_op_defRichard Henderson1-124/+154
Use a switch instead of searching a table. Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-05tcg: Implement implicit ordering semanticsPranith Kumar1-0/+16
Currently, we cannot use mttcg for running strong memory model guests on weak memory model hosts due to missing ordering semantics. We implicitly generate fence instructions for stronger guests if an ordering mismatch is detected. We generate fences only for the orders for which fence instructions are necessary, for example a fence is not necessary between a store and a subsequent load on x86 since its absence in the guest binary tells that ordering need not be ensured. Also note that if we find multiple subsequent fence instructions in the generated IR, we combine them in the TCG optimization pass. This patch allows us to boot an x86 guest on ARM64 hosts using mttcg. Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20170829063313.10237-4-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-05tcg: Add tcg target default memory orderingPranith Kumar6-0/+12
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20170829063313.10237-3-bobby.prani@gmail.com> [rth: Dropped ia64 hunk] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-05tcg: Remove support for ia64 as hostRichard Henderson2-2680/+0
We threatened to remove ia64 as host in v2.9.0. Its time has now come. There are still some usages of defined(__ia64__) throughout the source code that would be triggered if one were to enable TCI on an ia64 host. Leave those alone for now. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-08-03tcg: Increase minimum alignment from tcg_malloc to 8Richard Henderson1-1/+4
For a 64-bit ILP32 host, aligning to sizeof(long) is not enough. Guess the minimum for any host is 8, as that covers uint64_t. Qemu doesn't use a host long double or host vectors, except in extremely limited circumstances. Fixes a bus error for a sparc v8plus host. Signed-off-by: Richard Henderson <rth@twiddle.net>
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