From a1cf8be550c65d316ad666c778e21773ce113eb8 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 4 Aug 2014 18:13:11 +0100 Subject: sun4u: switch second PCI-ebus bridge BAR over to PCI IO space The ebus is the sun4u equivalent of the old ISA bus which is already mapped at the beginning of PCI IO space within QEMU. NetBSD attempts to find the physical addresses of devices connected to the ebus by parsing the BARs of the PCI-ebus bridge and using the base address found by matching both the address space type and range for a particular ebus address. Since the second PCI-ebus bridge BAR is already aliased onto IO space, switch the BAR over to match and reduce the size to 0x1000 which is enough to cover all the legacy ioport devices whilst leaving the remaining IO space for other PCI devices. This allows NetBSD SPARC64 to correctly detect and access devices on the ebus. Signed-off-by: Mark Cave-Ayland --- hw/sparc64/sun4u.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 33c311bf28..b9f3bee9ae 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -609,8 +609,8 @@ pci_ebus_init1(PCIDevice *pci_dev) 0, 0x1000000); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), - 0, 0x800000); - pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1); + 0, 0x1000); + pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); return 0; } -- cgit v1.2.1 From b87b0644bc04dd88c38cf2eb2f59756d59808204 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 11 Aug 2014 12:22:52 +0100 Subject: apb: add IOMMU flush register implementation The IOMMU flush register is a write-only register used to remove entries from the hardware TLB. Allow guest writes to this register as a no-op, and return a value of 0 for reads. This fixes IOMMU DMA operations under NetBSD SPARC64. Signed-off-by: Mark Cave-Ayland --- hw/pci-host/apb.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index d238a84f95..60bd81e477 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -94,6 +94,7 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) #define IOMMU_CTRL_TSB_SHIFT 16 #define IOMMU_BASE 0x8 +#define IOMMU_FLUSH 0x10 #define IOMMU_TTE_DATA_V (1ULL << 63) #define IOMMU_TTE_DATA_SIZE (1ULL << 61) @@ -352,6 +353,9 @@ static void iommu_config_write(void *opaque, hwaddr addr, is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL; is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL; break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + break; default: qemu_log_mask(LOG_UNIMP, "apb iommu: Unimplemented register write " @@ -387,6 +391,10 @@ static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size) case IOMMU_BASE + 0x4: val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + val = 0; + break; default: qemu_log_mask(LOG_UNIMP, "apb iommu: Unimplemented register read " @@ -415,7 +423,7 @@ static void apb_config_writel (void *opaque, hwaddr addr, /* XXX: not implemented yet */ break; case 0x200 ... 0x217: /* IOMMU */ - iommu_config_write(is, (addr & 0xf), val, size); + iommu_config_write(is, (addr & 0x1f), val, size); break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { @@ -497,7 +505,7 @@ static uint64_t apb_config_readl (void *opaque, /* XXX: not implemented yet */ break; case 0x200 ... 0x217: /* IOMMU */ - val = iommu_config_read(is, (addr & 0xf), size); + val = iommu_config_read(is, (addr & 0x1f), size); break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { -- cgit v1.2.1 From 2a5fade753e66ae68f0131962391cd78b99afa53 Mon Sep 17 00:00:00 2001 From: Artyom Tarasenko Date: Fri, 8 Aug 2014 22:48:00 +0200 Subject: target-sparc64: implement Short Floating-Point Store Instructions Implement Short Floating-Point Store Instructions as described in the chapter 13.5.2 of UltraSPARC-IIi User's Manual. Particularly this instructions are used by NetBSD 4.0.1+ /sparc64 Signed-off-by: Artyom Tarasenko Signed-off-by: Mark Cave-Ayland --- target-sparc/ldst_helper.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 03bd9f9706..1a62e193bd 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -2154,7 +2154,6 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, unsigned int i; target_ulong val; - helper_check_align(env, addr, 3); addr = asi_address_mask(env, asi, addr); switch (asi) { @@ -2191,8 +2190,22 @@ void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8); } + return; + case 0xd2: /* 16-bit floating point load primary */ + case 0xd3: /* 16-bit floating point load secondary */ + case 0xda: /* 16-bit floating point load primary, LE */ + case 0xdb: /* 16-bit floating point load secondary, LE */ + helper_check_align(env, addr, 1); + /* Fall through */ + case 0xd0: /* 8-bit floating point load primary */ + case 0xd1: /* 8-bit floating point load secondary */ + case 0xd8: /* 8-bit floating point load primary, LE */ + case 0xd9: /* 8-bit floating point load secondary, LE */ + val = env->fpr[rd / 2].l.lower; + helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1); return; default: + helper_check_align(env, addr, 3); break; } -- cgit v1.2.1