From 35b961cf8d8a38e51a05dd9e540d1ddc6e66ffc3 Mon Sep 17 00:00:00 2001 From: bellard Date: Wed, 9 Aug 2006 21:55:55 +0000 Subject: indent git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2104 c046a42c-6fe2-441c-8c8c-71466251a162 --- hw/lance.c | 208 ++++++++++++++++++++++++++++++++----------------------------- 1 file changed, 110 insertions(+), 98 deletions(-) diff --git a/hw/lance.c b/hw/lance.c index d1679375d0..cf02333dd5 100644 --- a/hw/lance.c +++ b/hw/lance.c @@ -48,7 +48,7 @@ do { printf("LANCE: " fmt , ##args); } while (0) #define LE_RDP 0 #define LE_RAP 1 -#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */ +#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */ #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */ #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */ @@ -67,36 +67,36 @@ do { printf("LANCE: " fmt , ##args); } while (0) #define LE_C0_STRT 0x0002 /* Start the card */ #define LE_C0_INIT 0x0001 /* Init the card */ -#define LE_C3_BSWP 0x4 /* SWAP */ +#define LE_C3_BSWP 0x4 /* SWAP */ #define LE_C3_ACON 0x2 /* ALE Control */ #define LE_C3_BCON 0x1 /* Byte control */ /* Receive message descriptor 1 */ -#define LE_R1_OWN 0x80 /* Who owns the entry */ -#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */ -#define LE_R1_FRA 0x20 /* FRA: Frame error */ -#define LE_R1_OFL 0x10 /* OFL: Frame overflow */ -#define LE_R1_CRC 0x08 /* CRC error */ -#define LE_R1_BUF 0x04 /* BUF: Buffer error */ -#define LE_R1_SOP 0x02 /* Start of packet */ -#define LE_R1_EOP 0x01 /* End of packet */ -#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ - -#define LE_T1_OWN 0x80 /* Lance owns the packet */ -#define LE_T1_ERR 0x40 /* Error summary */ -#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */ -#define LE_T1_EONE 0x08 /* Error: one retry needed */ -#define LE_T1_EDEF 0x04 /* Error: deferred */ -#define LE_T1_SOP 0x02 /* Start of packet */ -#define LE_T1_EOP 0x01 /* End of packet */ +#define LE_R1_OWN 0x80 /* Who owns the entry */ +#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */ +#define LE_R1_FRA 0x20 /* FRA: Frame error */ +#define LE_R1_OFL 0x10 /* OFL: Frame overflow */ +#define LE_R1_CRC 0x08 /* CRC error */ +#define LE_R1_BUF 0x04 /* BUF: Buffer error */ +#define LE_R1_SOP 0x02 /* Start of packet */ +#define LE_R1_EOP 0x01 /* End of packet */ +#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ + +#define LE_T1_OWN 0x80 /* Lance owns the packet */ +#define LE_T1_ERR 0x40 /* Error summary */ +#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */ +#define LE_T1_EONE 0x08 /* Error: one retry needed */ +#define LE_T1_EDEF 0x04 /* Error: deferred */ +#define LE_T1_SOP 0x02 /* Start of packet */ +#define LE_T1_EOP 0x01 /* End of packet */ #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ -#define LE_T3_BUF 0x8000 /* Buffer error */ -#define LE_T3_UFL 0x4000 /* Error underflow */ -#define LE_T3_LCOL 0x1000 /* Error late collision */ -#define LE_T3_CLOS 0x0800 /* Error carrier loss */ -#define LE_T3_RTY 0x0400 /* Error retry */ -#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */ +#define LE_T3_BUF 0x8000 /* Buffer error */ +#define LE_T3_UFL 0x4000 /* Error underflow */ +#define LE_T3_LCOL 0x1000 /* Error late collision */ +#define LE_T3_CLOS 0x0800 /* Error carrier loss */ +#define LE_T3_RTY 0x0400 /* Error retry */ +#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */ #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS)) #define TX_RING_MOD_MASK (TX_RING_SIZE - 1) @@ -111,43 +111,43 @@ do { printf("LANCE: " fmt , ##args); } while (0) #define TX_BUFF_SIZE PKT_BUF_SZ struct lance_rx_desc { - unsigned short rmd0; /* low address of packet */ - unsigned char rmd1_bits; /* descriptor bits */ - unsigned char rmd1_hadr; /* high address of packet */ - short length; /* This length is 2s complement (negative)! - * Buffer length - */ - unsigned short mblength; /* This is the actual number of bytes received */ + unsigned short rmd0; /* low address of packet */ + unsigned char rmd1_bits; /* descriptor bits */ + unsigned char rmd1_hadr; /* high address of packet */ + short length; /* This length is 2s complement (negative)! + * Buffer length + */ + unsigned short mblength; /* This is the actual number of bytes received */ }; struct lance_tx_desc { - unsigned short tmd0; /* low address of packet */ - unsigned char tmd1_bits; /* descriptor bits */ - unsigned char tmd1_hadr; /* high address of packet */ - short length; /* Length is 2s complement (negative)! */ - unsigned short misc; + unsigned short tmd0; /* low address of packet */ + unsigned char tmd1_bits; /* descriptor bits */ + unsigned char tmd1_hadr; /* high address of packet */ + short length; /* Length is 2s complement (negative)! */ + unsigned short misc; }; /* The LANCE initialization block, described in databook. */ /* On the Sparc, this block should be on a DMA region */ struct lance_init_block { - unsigned short mode; /* Pre-set mode (reg. 15) */ - unsigned char phys_addr[6]; /* Physical ethernet address */ - unsigned filter[2]; /* Multicast filter. */ - - /* Receive and transmit ring base, along with extra bits. */ - unsigned short rx_ptr; /* receive descriptor addr */ - unsigned short rx_len; /* receive len and high addr */ - unsigned short tx_ptr; /* transmit descriptor addr */ - unsigned short tx_len; /* transmit len and high addr */ - - /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */ - struct lance_rx_desc brx_ring[RX_RING_SIZE]; - struct lance_tx_desc btx_ring[TX_RING_SIZE]; - - char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE]; - char pad[2]; /* align rx_buf for copy_and_sum(). */ - char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE]; + unsigned short mode; /* Pre-set mode (reg. 15) */ + unsigned char phys_addr[6]; /* Physical ethernet address */ + unsigned filter[2]; /* Multicast filter. */ + + /* Receive and transmit ring base, along with extra bits. */ + unsigned short rx_ptr; /* receive descriptor addr */ + unsigned short rx_len; /* receive len and high addr */ + unsigned short tx_ptr; /* transmit descriptor addr */ + unsigned short tx_len; /* transmit len and high addr */ + + /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */ + struct lance_rx_desc brx_ring[RX_RING_SIZE]; + struct lance_tx_desc btx_ring[TX_RING_SIZE]; + + char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE]; + char pad[2]; /* align rx_buf for copy_and_sum(). */ + char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE]; }; #define LEDMA_REGS 4 @@ -155,11 +155,11 @@ struct lance_init_block { typedef struct LANCEState { VLANClientState *vc; - uint8_t macaddr[6]; /* init mac address */ + uint8_t macaddr[6]; /* init mac address */ uint32_t leptr; uint16_t addr; uint16_t regs[LE_NREGS]; - uint8_t phys[6]; /* mac address */ + uint8_t phys[6]; /* mac address */ int irq; unsigned int rxptr, txptr; uint32_t ledmaregs[LEDMA_REGS]; @@ -192,13 +192,14 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) DPRINTF("read areg = %4.4x\n", s->addr); return s->addr; default: - DPRINTF("read unknown(%d)\n", saddr>>1); + DPRINTF("read unknown(%d)\n", saddr >> 1); break; } return 0; } -static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void lance_mem_writew(void *opaque, target_phys_addr_t addr, + uint32_t val) { LANCEState *s = opaque; uint32_t saddr; @@ -208,7 +209,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val switch (saddr >> 1) { case LE_RDP: DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val); - switch(s->addr) { + switch (s->addr) { case LE_CSR0: if (val & LE_C0_STOP) { s->regs[LE_CSR0] = LE_C0_STOP; @@ -235,8 +236,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val if (val & LE_C0_INIT) { reg |= LE_C0_IDON | LE_C0_INIT; reg &= ~LE_C0_STOP; - } - else if (val & LE_C0_STRT) { + } else if (val & LE_C0_STRT) { reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON; reg &= ~LE_C0_STOP; } @@ -262,7 +262,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val s->addr = val; break; default: - DPRINTF("write unknown(%d) = %4.4x\n", saddr>>1, val); + DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val); break; } lance_send(s); @@ -288,7 +288,7 @@ static int lance_can_receive(void *opaque) return 1; } -static void lance_receive(void *opaque, const uint8_t *buf, int size) +static void lance_receive(void *opaque, const uint8_t * buf, int size) { LANCEState *s = opaque; uint32_t dmaptr = s->leptr + s->ledmaregs[3]; @@ -304,16 +304,21 @@ static void lance_receive(void *opaque, const uint8_t *buf, int size) ib = (void *) iommu_translate(dmaptr); old_rxptr = s->rxptr; - for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) { - cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1); + for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); + i = (i + 1) & RX_RING_MOD_MASK) { + cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits, + (void *) &temp8, 1); if (temp8 == (LE_R1_OWN)) { s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK; temp16 = size + 4; bswap16s(&temp16); - cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp16, 2); - cpu_physical_memory_write((uint32_t)&ib->rx_buf[i], buf, size); + cpu_physical_memory_write((uint32_t) & ib->brx_ring[i]. + mblength, (void *) &temp16, 2); + cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf, + size); temp8 = LE_R1_POK; - cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1); + cpu_physical_memory_write((uint32_t) & ib->brx_ring[i]. + rmd1_bits, (void *) &temp8, 1); s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR; if (s->regs[LE_CSR0] & LE_C0_INEA) pic_set_irq(s->irq, 1); @@ -339,19 +344,25 @@ static void lance_send(void *opaque) ib = (void *) iommu_translate(dmaptr); - DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr, ib, &ib->btx_ring); + DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", + dmaptr, ib, &ib->btx_ring); old_txptr = s->txptr; - for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) { - cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1); - if (temp8 == (LE_T1_POK|LE_T1_OWN)) { - cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp16, 2); + for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); + i = (i + 1) & TX_RING_MOD_MASK) { + cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits, + (void *) &temp8, 1); + if (temp8 == (LE_T1_POK | LE_T1_OWN)) { + cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length, + (void *) &temp16, 2); bswap16s(&temp16); temp16 = (~temp16) + 1; - cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp16); + cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf, + temp16); DPRINTF("sending packet, len %d\n", temp16); qemu_send_packet(s->vc, pkt_buf, temp16); temp8 = LE_T1_POK; - cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1); + cpu_physical_memory_write((uint32_t) & ib->btx_ring[i]. + tmd1_bits, (void *) &temp8, 1); s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK; s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR; } @@ -369,7 +380,8 @@ static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr) return s->ledmaregs[saddr]; } -static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, + uint32_t val) { LANCEState *s = opaque; uint32_t saddr; @@ -390,73 +402,73 @@ static CPUWriteMemoryFunc *ledma_mem_write[3] = { ledma_mem_writel, }; -static void lance_save(QEMUFile *f, void *opaque) +static void lance_save(QEMUFile * f, void *opaque) { LANCEState *s = opaque; int i; - + qemu_put_be32s(f, &s->leptr); qemu_put_be16s(f, &s->addr); - for (i = 0; i < LE_NREGS; i ++) + for (i = 0; i < LE_NREGS; i++) qemu_put_be16s(f, &s->regs[i]); qemu_put_buffer(f, s->phys, 6); qemu_put_be32s(f, &s->irq); - for (i = 0; i < LEDMA_REGS; i ++) + for (i = 0; i < LEDMA_REGS; i++) qemu_put_be32s(f, &s->ledmaregs[i]); } -static int lance_load(QEMUFile *f, void *opaque, int version_id) +static int lance_load(QEMUFile * f, void *opaque, int version_id) { LANCEState *s = opaque; int i; - + if (version_id != 1) - return -EINVAL; + return -EINVAL; qemu_get_be32s(f, &s->leptr); qemu_get_be16s(f, &s->addr); - for (i = 0; i < LE_NREGS; i ++) + for (i = 0; i < LE_NREGS; i++) qemu_get_be16s(f, &s->regs[i]); qemu_get_buffer(f, s->phys, 6); qemu_get_be32s(f, &s->irq); - for (i = 0; i < LEDMA_REGS; i ++) + for (i = 0; i < LEDMA_REGS; i++) qemu_get_be32s(f, &s->ledmaregs[i]); return 0; } -void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr) +void lance_init(NICInfo * nd, int irq, uint32_t leaddr, uint32_t ledaddr) { LANCEState *s; int lance_io_memory, ledma_io_memory; s = qemu_mallocz(sizeof(LANCEState)); if (!s) - return; + return; s->irq = irq; - lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s); + lance_io_memory = + cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s); cpu_register_physical_memory(leaddr, 4, lance_io_memory); - ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s); + ledma_io_memory = + cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s); cpu_register_physical_memory(ledaddr, 16, ledma_io_memory); memcpy(s->macaddr, nd->macaddr, 6); lance_reset(s); - s->vc = qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, s); + s->vc = + qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, + s); snprintf(s->vc->info_str, sizeof(s->vc->info_str), - "lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x", - s->macaddr[0], - s->macaddr[1], - s->macaddr[2], - s->macaddr[3], - s->macaddr[4], - s->macaddr[5]); + "lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x", + s->macaddr[0], + s->macaddr[1], + s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]); register_savevm("lance", leaddr, 1, lance_save, lance_load, s); qemu_register_reset(lance_reset, s); } - -- cgit v1.2.1