From 4f89b41c28a17739c4fd40886542e3cb8c7a15a3 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Sat, 14 Jan 2017 19:58:55 -0800 Subject: target/xtensa: tests: replace hardcoded interrupt masks Signed-off-by: Max Filippov --- tests/tcg/xtensa/test_timer.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S index 9e6012d7fd..844c0327aa 100644 --- a/tests/tcg/xtensa/test_timer.S +++ b/tests/tcg/xtensa/test_timer.S @@ -59,7 +59,7 @@ test ccompare0_interrupt rsr a2, interrupt assert eqi, a2, 0 - movi a2, 0x40 + movi a2, 1 << XCHAL_TIMER0_INTERRUPT wsr a2, intenable rsil a2, 0 loop a3, 1f @@ -87,7 +87,7 @@ test ccompare1_interrupt rsync rsr a2, interrupt assert eqi, a2, 0 - movi a2, 0x400 + movi a2, 1 << XCHAL_TIMER1_INTERRUPT wsr a2, intenable rsil a2, 2 loop a3, 1f @@ -113,7 +113,7 @@ test ccompare2_interrupt rsync rsr a2, interrupt assert eqi, a2, 0 - movi a2, 0x2000 + movi a2, 1 << XCHAL_TIMER2_INTERRUPT wsr a2, intenable rsil a2, 4 loop a3, 1f @@ -141,7 +141,7 @@ test ccompare_interrupt_masked rsr a2, interrupt assert eqi, a2, 0 - movi a2, 0x40 + movi a2, 1 << XCHAL_TIMER0_INTERRUPT wsr a2, intenable rsil a2, 0 loop a3, 1f @@ -171,7 +171,7 @@ test ccompare_interrupt_masked_waiti rsr a2, interrupt assert eqi, a2, 0 - movi a2, 0x40 + movi a2, 1 << XCHAL_TIMER0_INTERRUPT wsr a2, intenable waiti 0 test_fail -- cgit v1.2.1