From a0762859ae2aae2e221c59e2541f964f1350d68b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Sun, 16 Jun 2013 07:28:50 +0200 Subject: log: Change log_cpu_state[_mask]() argument to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no longer needed. Add documentation and make the functions available through qemu/log.h outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h was not yet possible due to convoluted include paths, so that some devices grow an implicit and unneeded dependency on qom/cpu.h for now. Acked-by: Michael Walle (for lm32) Reviewed-by: Richard Henderson [AF: Simplified mb_cpu_do_interrupt() and do_interrupt_all() changes] Signed-off-by: Andreas Färber --- cpu-exec.c | 6 +++--- exec.c | 2 +- include/qemu/log.h | 26 +++++++++++++++++++++----- linux-user/main.c | 5 +++-- target-arm/cpu.c | 2 +- target-cris/cpu.c | 2 +- target-i386/cpu.c | 2 +- target-i386/seg_helper.c | 4 ++-- target-i386/smm_helper.c | 5 +++-- target-lm32/cpu.c | 2 +- target-lm32/helper.c | 4 ++-- target-m68k/cpu.c | 2 +- target-microblaze/cpu.c | 2 +- target-microblaze/helper.c | 12 ++++++------ target-microblaze/translate.c | 2 +- target-mips/cpu.c | 2 +- target-mips/helper.c | 2 +- target-moxie/cpu.c | 2 +- target-openrisc/cpu.c | 2 +- target-openrisc/translate.c | 2 +- target-ppc/mmu-hash32.c | 2 +- target-ppc/mmu-hash64.c | 2 +- target-ppc/mmu_helper.c | 2 +- target-ppc/translate_init.c | 2 +- target-s390x/cpu.c | 2 +- target-sh4/cpu.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/cpu.c | 2 +- target-sparc/int32_helper.c | 2 +- target-sparc/int64_helper.c | 2 +- 30 files changed, 63 insertions(+), 45 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 58a0674823..6c784a7e09 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -577,15 +577,15 @@ int cpu_exec(CPUArchState *env) if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { /* restore flags in standard format */ #if defined(TARGET_I386) - log_cpu_state(env, CPU_DUMP_CCOP); + log_cpu_state(cpu, CPU_DUMP_CCOP); #elif defined(TARGET_M68K) cpu_m68k_flush_flags(env, env->cc_op); env->cc_op = CC_OP_FLAGS; env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4); - log_cpu_state(env, 0); + log_cpu_state(cpu, 0); #else - log_cpu_state(env, 0); + log_cpu_state(cpu, 0); #endif } #endif /* DEBUG_DISAS */ diff --git a/exec.c b/exec.c index 61b094a99b..f01e3b684f 100644 --- a/exec.c +++ b/exec.c @@ -617,7 +617,7 @@ void cpu_abort(CPUArchState *env, const char *fmt, ...) qemu_log("qemu: fatal: "); qemu_log_vprintf(fmt, ap2); qemu_log("\n"); - log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP); + log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); qemu_log_flush(); qemu_log_close(); } diff --git a/include/qemu/log.h b/include/qemu/log.h index a9cf2146c5..d5154246e6 100644 --- a/include/qemu/log.h +++ b/include/qemu/log.h @@ -5,6 +5,7 @@ #include #include #include "qemu/compiler.h" +#include "qom/cpu.h" #ifdef NEED_CPU_H #include "disas/disas.h" #endif @@ -70,22 +71,37 @@ void GCC_FMT_ATTR(2, 3) qemu_log_mask(int mask, const char *fmt, ...); /* Special cases: */ -#ifdef NEED_CPU_H /* cpu_dump_state() logging functions: */ -static inline void log_cpu_state(CPUArchState *env1, int flags) +/** + * log_cpu_state: + * @cpu: The CPU whose state is to be logged. + * @flags: Flags what to log. + * + * Logs the output of cpu_dump_state(). + */ +static inline void log_cpu_state(CPUState *cpu, int flags) { if (qemu_log_enabled()) { - cpu_dump_state(ENV_GET_CPU(env1), qemu_logfile, fprintf, flags); + cpu_dump_state(cpu, qemu_logfile, fprintf, flags); } } -static inline void log_cpu_state_mask(int mask, CPUArchState *env1, int flags) +/** + * log_cpu_state_mask: + * @mask: Mask when to log. + * @cpu: The CPU whose state is to be logged. + * @flags: Flags what to log. + * + * Logs the output of cpu_dump_state() if loglevel includes @mask. + */ +static inline void log_cpu_state_mask(int mask, CPUState *cpu, int flags) { if (qemu_loglevel & mask) { - log_cpu_state(env1, flags); + log_cpu_state(cpu, flags); } } +#ifdef NEED_CPU_H /* disas() and target_disas() to qemu_logfile: */ static inline void log_target_disas(CPUArchState *env, target_ulong start, target_ulong len, int flags) diff --git a/linux-user/main.c b/linux-user/main.c index 67ea9ba841..7f15d3da2b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1302,11 +1302,12 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) #define EXCP_DUMP(env, fmt, ...) \ do { \ + CPUState *cs = ENV_GET_CPU(env); \ fprintf(stderr, fmt , ## __VA_ARGS__); \ - cpu_dump_state(ENV_GET_CPU(env), stderr, fprintf, 0); \ + cpu_dump_state(cs, stderr, fprintf, 0); \ qemu_log(fmt, ## __VA_ARGS__); \ if (qemu_log_enabled()) { \ - log_cpu_state(env, 0); \ + log_cpu_state(cs, 0); \ } \ } while (0) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1bc227e9a6..84974a9a35 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -65,7 +65,7 @@ static void arm_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } acc->parent_reset(s); diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 6a3bdf00f8..f6c4f3f869 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -36,7 +36,7 @@ static void cris_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } ccc->parent_reset(s); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b7416fea35..82a451b4c1 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2177,7 +2177,7 @@ static void x86_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP); + log_cpu_state(s, CPU_DUMP_FPU | CPU_DUMP_CCOP); } xcc->parent_reset(s); diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 92caa84838..fc7ffad8c5 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -31,7 +31,7 @@ #ifdef DEBUG_PCALL # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__) # define LOG_PCALL_STATE(env) \ - log_cpu_state_mask(CPU_LOG_PCALL, (env), CPU_DUMP_CCOP) + log_cpu_state_mask(CPU_LOG_PCALL, CPU(x86_env_get_cpu(env)), CPU_DUMP_CCOP) #else # define LOG_PCALL(...) do { } while (0) # define LOG_PCALL_STATE(env) do { } while (0) @@ -1182,7 +1182,7 @@ static void do_interrupt_all(X86CPU *cpu, int intno, int is_int, qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]); } qemu_log("\n"); - log_cpu_state(env, CPU_DUMP_CCOP); + log_cpu_state(CPU(cpu), CPU_DUMP_CCOP); #if 0 { int i; diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 78abe5b83f..6cb45511b8 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -48,7 +48,7 @@ void do_smm_enter(X86CPU *cpu) int i, offset; qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); - log_cpu_state_mask(CPU_LOG_INT, env, CPU_DUMP_CCOP); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); env->hflags |= HF_SMM_MASK; cpu_smm_update(env); @@ -180,6 +180,7 @@ void do_smm_enter(X86CPU *cpu) void helper_rsm(CPUX86State *env) { + X86CPU *cpu = x86_env_get_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; @@ -296,7 +297,7 @@ void helper_rsm(CPUX86State *env) cpu_smm_update(env); qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n"); - log_cpu_state_mask(CPU_LOG_INT, env, CPU_DUMP_CCOP); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 02f8436bff..6e44d452fe 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -31,7 +31,7 @@ static void lm32_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } lcc->parent_reset(s); diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 03fa5fbe28..615b44e5be 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -70,7 +70,7 @@ void lm32_cpu_do_interrupt(CPUState *cs) } else { env->pc = env->eba + (env->exception_index * 32); } - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; case EXCP_BREAKPOINT: case EXCP_WATCHPOINT: @@ -79,7 +79,7 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; env->ie &= ~IE_IE; env->pc = env->deba + (env->exception_index * 32); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; default: cpu_abort(env, "unhandled exception type=%d\n", diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 799869ff97..c9ac30f7ec 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -37,7 +37,7 @@ static void m68k_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index a0fcdf4464..d93519e465 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -35,7 +35,7 @@ static void mb_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 01d4bbfe92..c6c96d4488 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=%x ear=%x esr=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; @@ -175,7 +175,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "bimm exception at pc=%x iflags=%x\n", env->sregs[SR_PC], env->iflags); env->regs[17] -= 4; - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); } } else if (env->iflags & IMM_FLAG) { D(qemu_log("IMM_FLAG set at exception\n")); @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%x ear=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags, sym); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); } } #endif @@ -236,7 +236,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] = env->sregs[SR_PC]; env->sregs[SR_PC] = cpu->base_vectors + 0x10; - //log_cpu_state_mask(CPU_LOG_INT, env, 0); + //log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; case EXCP_BREAK: @@ -247,7 +247,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index b5cb14163a..eba255b7c6 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1777,7 +1777,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { #if !SIM_COMPAT qemu_log("--------------\n"); - log_cpu_state(env, 0); + log_cpu_state(CPU(cpu), 0); #endif } diff --git a/target-mips/cpu.c b/target-mips/cpu.c index b61e207317..cab9572727 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -31,7 +31,7 @@ static void mips_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-mips/helper.c b/target-mips/helper.c index 36929ddee7..6983b92a11 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -276,7 +276,7 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, int ret = 0; #if 0 - log_cpu_state(env, 0); + log_cpu_state(CPU(mips_env_get_cpu(env)), 0); #endif qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n", __func__, env->active_tc.PC, address, rw, mmu_idx); diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index f3c0d22141..7314d4bcf9 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -30,7 +30,7 @@ static void moxie_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index d38c28b2f3..0dc60c9f7e 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -28,7 +28,7 @@ static void openrisc_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(&cpu->env, 0); + log_cpu_state(s, 0); } occ->parent_reset(s); diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index c59fd0208d..f222834fc3 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1684,7 +1684,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, dc->singlestep_enabled = cpu->env.singlestep_enabled; if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("-----------------------------------------\n"); - log_cpu_state(&cpu->env, 0); + log_cpu_state(CPU(cpu), 0); } next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index f6adf2245e..b5ebe07c9d 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -29,7 +29,7 @@ #ifdef DEBUG_MMU # define LOG_MMU(...) qemu_log(__VA_ARGS__) -# define LOG_MMU_STATE(env) log_cpu_state((env), 0) +# define LOG_MMU_STATE(env) log_cpu_state(CPU(ppc_env_get_cpu(env)), 0) #else # define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(...) do { } while (0) diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 5c67ec3e9c..759cef3714 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -28,7 +28,7 @@ #ifdef DEBUG_MMU # define LOG_MMU(...) qemu_log(__VA_ARGS__) -# define LOG_MMU_STATE(env) log_cpu_state((env), 0) +# define LOG_MMU_STATE(env) log_cpu_state(CPU(ppc_env_get_cpu(env)), 0) #else # define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(...) do { } while (0) diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index e4e111c555..413e95bc56 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -32,7 +32,7 @@ #ifdef DEBUG_MMU # define LOG_MMU(...) qemu_log(__VA_ARGS__) -# define LOG_MMU_STATE(env) log_cpu_state((env), 0) +# define LOG_MMU_STATE(env) log_cpu_state(CPU(ppc_env_get_cpu(env)), 0) #else # define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(...) do { } while (0) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 50e0ee5735..43eec67e49 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8173,7 +8173,7 @@ static void ppc_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } pcc->parent_reset(s); diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index c3697cd943..732d393209 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -67,7 +67,7 @@ static void s390_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } s390_del_running_cpu(cpu); diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index e73915693f..653acec582 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -33,7 +33,7 @@ static void superh_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } scc->parent_reset(s); diff --git a/target-sh4/helper.c b/target-sh4/helper.c index ce10ca84ee..cb6a2d28bd 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -159,7 +159,7 @@ void superh_cpu_do_interrupt(CPUState *cs) } qemu_log("exception 0x%03x [%s] raised\n", irq_vector, expname); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); } env->ssr = env->sr; diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 65ae6f73bf..4cbb2063d5 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -32,7 +32,7 @@ static void sparc_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } scc->parent_reset(s); diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index 722146065a..d5322380cd 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -86,7 +86,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) } qemu_log("%6d: %s (v=%02x)\n", count, name, intno); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); #if 0 { int i; diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index f411884c6e..bf7dd86ab8 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -92,7 +92,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) } qemu_log("%6d: %s (v=%04x)\n", count, name, intno); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); #if 0 { int i; -- cgit v1.2.1