From a1df76da57aa8772a75e7c49f8e3829d07b4c46c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 14 Jun 2016 14:35:20 +0200 Subject: serial: remove watch on reset Otherwise, this can cause serial_xmit to be entered with LSR.TEMT=0, which is invalid and causes an assertion failure. Reported-by: Bret Ketchum Tested-by: Bret Ketchum Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Paolo Bonzini --- hw/char/serial.c | 16 ++++++++++++---- include/hw/char/serial.h | 1 + 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/char/serial.c b/hw/char/serial.c index 0b09094c0c..af39e8f867 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -228,6 +228,7 @@ static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond, void *opaque) { SerialState *s = opaque; + s->watch_tag = 0; serial_xmit(s); return FALSE; } @@ -258,10 +259,12 @@ static void serial_xmit(SerialState *s) if (s->mcr & UART_MCR_LOOP) { /* in loopback mode, say that we just received a char */ serial_receive1(s, &s->tsr, 1); - } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { - if (s->tsr_retry < MAX_XMIT_RETRY && - qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP, - serial_watch_cb, s) > 0) { + } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1 && + s->tsr_retry < MAX_XMIT_RETRY) { + assert(s->watch_tag == 0); + s->watch_tag = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP, + serial_watch_cb, s); + if (s->watch_tag > 0) { s->tsr_retry++; return; } @@ -821,6 +824,11 @@ static void serial_reset(void *opaque) { SerialState *s = opaque; + if (s->watch_tag > 0) { + g_source_remove(s->watch_tag); + s->watch_tag = 0; + } + s->rbr = 0; s->ier = 0; s->iir = UART_IIR_NO_INT; diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h index 6a322eb22e..9feddc613c 100644 --- a/include/hw/char/serial.h +++ b/include/hw/char/serial.h @@ -56,6 +56,7 @@ struct SerialState { int it_shift; int baudbase; uint32_t tsr_retry; + guint watch_tag; uint32_t wakeup; /* Time when the last byte was successfully sent out of the tsr */ -- cgit v1.2.1