From d437262fa8edd0d9fbe038a515dda3dbf7c5bb54 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 27 Dec 2016 14:59:24 +0000 Subject: target-arm: Fix aarch64 vec_reg_offset Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used for a big-endian host doesn't do what's intended. Fix this by adding in the vfp.regs offset after computing the inter-register offset. Signed-off-by: Richard Henderson Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit 416d72b97b01d6cb769ad0fd0e10614583354a45) Signed-off-by: Michael Roth --- target-arm/translate-a64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 434dae165e..f673d939e1 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -527,7 +527,7 @@ static inline void assert_fp_access_checked(DisasContext *s) static inline int vec_reg_offset(DisasContext *s, int regno, int element, TCGMemOp size) { - int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); + int offs = 0; #ifdef HOST_WORDS_BIGENDIAN /* This is complicated slightly because vfp.regs[2n] is * still the low half and vfp.regs[2n+1] the high half @@ -540,6 +540,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno, #else offs += element * (1 << size); #endif + offs += offsetof(CPUARMState, vfp.regs[regno * 2]); assert_fp_access_checked(s); return offs; } -- cgit v1.2.1