From d77953b94ff20868b21796ee22ca57baa1cfc941 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 16 Jan 2013 19:29:31 +0100 Subject: cpu: Move current_tb field to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Explictly NULL it on CPU reset since it was located before breakpoints. Change vapic_report_tpr_access() argument to CPUState. This also resolves the use of void* for cpu.h independence. Change vAPIC patch_instruction() argument to X86CPU. Signed-off-by: Andreas Färber --- cputlb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'cputlb.c') diff --git a/cputlb.c b/cputlb.c index 88239c494a..aba7e44e1e 100644 --- a/cputlb.c +++ b/cputlb.c @@ -54,6 +54,7 @@ static const CPUTLBEntry s_cputlb_empty_entry = { */ void tlb_flush(CPUArchState *env, int flush_global) { + CPUState *cpu = ENV_GET_CPU(env); int i; #if defined(DEBUG_TLB) @@ -61,7 +62,7 @@ void tlb_flush(CPUArchState *env, int flush_global) #endif /* must reset current TB so that interrupts cannot modify the links while we are modifying them */ - env->current_tb = NULL; + cpu->current_tb = NULL; for (i = 0; i < CPU_TLB_SIZE; i++) { int mmu_idx; @@ -92,6 +93,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) void tlb_flush_page(CPUArchState *env, target_ulong addr) { + CPUState *cpu = ENV_GET_CPU(env); int i; int mmu_idx; @@ -110,7 +112,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr) } /* must reset current TB so that interrupts cannot modify the links while we are modifying them */ - env->current_tb = NULL; + cpu->current_tb = NULL; addr &= TARGET_PAGE_MASK; i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); -- cgit v1.2.1