From 1c38f84373dd0a360883a343f6f50a5c0c856dec Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Wed, 9 Apr 2014 14:53:24 -0500 Subject: monitor: QEMU Monitor Instruction Disassembly Incorrect for PowerPC LE Mode The monitor support for disassembling instructions does not honor the MSR[LE] bit for PowerPC processors. This change enhances the monitor_disas() routine by supporting a flag bit for Little Endian mode. Bit 16 is used since that bit was used in the analagous guest disassembly routine target_disas(). Also, to be consistent with target_disas(), the disassembler bfd_mach field can be passed in the flags argument. Reported-by: Anton Blanchard Signed-off-by: Tom Musta Reviewed-by: Peter Maydell Signed-off-by: Alexander Graf --- disas.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'disas.c') diff --git a/disas.c b/disas.c index 13971679bb..44a019a2e7 100644 --- a/disas.c +++ b/disas.c @@ -445,6 +445,8 @@ monitor_fprintf(FILE *stream, const char *fmt, ...) return 0; } +/* Disassembler for the monitor. + See target_disas for a description of flags. */ void monitor_disas(Monitor *mon, CPUArchState *env, target_ulong pc, int nb_insn, int is_physical, int flags) { @@ -485,11 +487,19 @@ void monitor_disas(Monitor *mon, CPUArchState *env, s.info.mach = bfd_mach_sparc_v9b; #endif #elif defined(TARGET_PPC) + if (flags & 0xFFFF) { + /* If we have a precise definition of the instruction set, use it. */ + s.info.mach = flags & 0xFFFF; + } else { #ifdef TARGET_PPC64 - s.info.mach = bfd_mach_ppc64; + s.info.mach = bfd_mach_ppc64; #else - s.info.mach = bfd_mach_ppc; + s.info.mach = bfd_mach_ppc; #endif + } + if ((flags >> 16) & 1) { + s.info.endian = BFD_ENDIAN_LITTLE; + } print_insn = print_insn_ppc; #elif defined(TARGET_M68K) print_insn = print_insn_m68k; -- cgit v1.2.1