From e4f308bbf9f360ee2af5b94b87aef170d8f20dc4 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Fri, 13 Dec 2013 17:22:06 +0100 Subject: acpi: piix4: remove not needed GPE0 mask Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized with all bits cleared and only QEMU itself can set bits there (i.e. guest can only clear bits in it). So guest can't triger SCI by setting _STS & _EN bits and there is not reason to mask out not supported _STS bits since they shouldn't be set by QEMU in the first place. Signed-off-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- hw/acpi/piix4.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'hw/acpi') diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 93849c8d36..b4caeab131 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -122,8 +122,7 @@ static void pm_update_sci(PIIX4PMState *s) ACPI_BITMASK_POWER_BUTTON_ENABLE | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | ACPI_BITMASK_TIMER_ENABLE)) != 0) || - (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) & - (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0); + ((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) != 0); qemu_set_irq(s->irq, sci_level); /* schedule a timer interruption if needed */ -- cgit v1.2.1 From 063135032808700a5a6b0b4a781f31252da2e762 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Fri, 13 Dec 2013 17:22:07 +0100 Subject: acpi: factor out common pm_update_sci() into acpi core ... and rename it into acpi_update_sci() since it changes SCI on only on PM registers status. Signed-off-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- hw/acpi/core.c | 18 ++++++++++++++++++ hw/acpi/ich9.c | 23 ++--------------------- hw/acpi/piix4.c | 26 ++++---------------------- 3 files changed, 24 insertions(+), 43 deletions(-) (limited to 'hw/acpi') diff --git a/hw/acpi/core.c b/hw/acpi/core.c index 58308a3406..79414b44c7 100644 --- a/hw/acpi/core.c +++ b/hw/acpi/core.c @@ -662,3 +662,21 @@ uint32_t acpi_gpe_ioport_readb(ACPIREGS *ar, uint32_t addr) return val; } + +void acpi_update_sci(ACPIREGS *regs, qemu_irq irq) +{ + int sci_level, pm1a_sts; + + pm1a_sts = acpi_pm1_evt_get_sts(regs); + + sci_level = ((pm1a_sts & + regs->pm1.evt.en & ACPI_BITMASK_PM1_COMMON_ENABLED) != 0) || + ((regs->gpe.sts[0] & regs->gpe.en[0]) != 0); + + qemu_set_irq(irq, sci_level); + + /* schedule a timer interruption if needed */ + acpi_pm_tmr_update(regs, + (regs->pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && + !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS)); +} diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 7e0429e0f9..dcdef7c923 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -44,29 +44,10 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) #define ICH9_DEBUG(fmt, ...) do { } while (0) #endif -static void pm_update_sci(ICH9LPCPMRegs *pm) -{ - int sci_level, pm1a_sts; - - pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs); - - sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) & - (ACPI_BITMASK_RT_CLOCK_ENABLE | - ACPI_BITMASK_POWER_BUTTON_ENABLE | - ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0); - qemu_set_irq(pm->irq, sci_level); - - /* schedule a timer interruption if needed */ - acpi_pm_tmr_update(&pm->acpi_regs, - (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && - !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS)); -} - static void ich9_pm_update_sci_fn(ACPIREGS *regs) { ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs); - pm_update_sci(pm); + acpi_update_sci(&pm->acpi_regs, pm->irq); } static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) @@ -193,7 +174,7 @@ static void pm_reset(void *opaque) pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN; } - pm_update_sci(pm); + acpi_update_sci(&pm->acpi_regs, pm->irq); } static void pm_powerdown_req(Notifier *n, void *opaque) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index b4caeab131..b6b97ceb63 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -112,28 +112,10 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, #define ACPI_ENABLE 0xf1 #define ACPI_DISABLE 0xf0 -static void pm_update_sci(PIIX4PMState *s) -{ - int sci_level, pmsts; - - pmsts = acpi_pm1_evt_get_sts(&s->ar); - sci_level = (((pmsts & s->ar.pm1.evt.en) & - (ACPI_BITMASK_RT_CLOCK_ENABLE | - ACPI_BITMASK_POWER_BUTTON_ENABLE | - ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0) || - ((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) != 0); - - qemu_set_irq(s->irq, sci_level); - /* schedule a timer interruption if needed */ - acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && - !(pmsts & ACPI_BITMASK_TIMER_STATUS)); -} - static void pm_tmr_timer(ACPIREGS *ar) { PIIX4PMState *s = container_of(ar, PIIX4PMState, ar); - pm_update_sci(s); + acpi_update_sci(&s->ar, s->irq); } static void apm_ctrl_changed(uint32_t val, void *arg) @@ -577,7 +559,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, PIIX4PMState *s = opaque; acpi_gpe_ioport_writeb(&s->ar, addr, val); - pm_update_sci(s); + acpi_update_sci(&s->ar, s->irq); PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); } @@ -693,7 +675,7 @@ static void piix4_cpu_hotplug_req(PIIX4PMState *s, CPUState *cpu, } else { g->sts[cpu_id / 8] &= ~(1 << (cpu_id % 8)); } - pm_update_sci(s); + acpi_update_sci(&s->ar, s->irq); } static void piix4_cpu_added_req(Notifier *n, void *opaque) @@ -767,7 +749,7 @@ static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, disable_device(s, slot); } - pm_update_sci(s); + acpi_update_sci(&s->ar, s->irq); return 0; } -- cgit v1.2.1 From 2c047956f3b27048883350c071bcd33ef8331d13 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Fri, 13 Dec 2013 17:22:10 +0100 Subject: acpi: ich9: allow guest to clear SCI rised by GPE it fixes IRQ storm since guest isn't able to lower SCI IRQ after it has been handled when it clears GPE event. Signed-off-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- hw/acpi/ich9.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/acpi') diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index dcdef7c923..30f0df8713 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -61,6 +61,7 @@ static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val, { ICH9LPCPMRegs *pm = opaque; acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); + acpi_update_sci(&pm->acpi_regs, pm->irq); } static const MemoryRegionOps ich9_gpe_ops = { -- cgit v1.2.1