From 327ed10fa2331384c1a58c794e0356e6d88089c8 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 26 Feb 2014 17:20:04 +0000 Subject: target-arm: Implement AArch64 TTBR* Implement the AArch64 TTBR* registers. For v7 these were already 64 bits to handle LPAE, but implemented as two separate uint32_t fields. Combine them into a single uint64_t which can be used for all purposes. Since this requires touching every use, take the opportunity to rename the field to the architectural name. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- hw/arm/pxa2xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/arm') diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 45a99c819d..5579036482 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; s->cpu->env.cp15.c1_sys = 0; s->cpu->env.cp15.c1_coproc = 0; - s->cpu->env.cp15.c2_base0 = 0; + s->cpu->env.cp15.ttbr0_el1 = 0; s->cpu->env.cp15.c3 = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ -- cgit v1.2.1