From 22709e90a270a36418f1b1d5d3277016eec1edc2 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 18 Mar 2014 13:18:39 -0500 Subject: pl011: reset the fifo when enabled or disabled Intermittent issues have been seen where no serial input occurs. It appears the pl011 gets in a state where the rx interrupt never fires because the rx interrupt only asserts when crossing the fifo trigger level. The fifo state appears to get out of sync when the pl011 is re-configured. This combined with the rx timeout interrupt not being modeled results in no more rx interrupts. Disabling the fifo is the recommended way to clear the tx fifo in the TRM (section 3.3.8). The behavior in this case for the rx fifo is undefined in the TRM, but having fifo contents to be maintained during configuration changes is not likely expected behavior. Reseting the fifo state when the fifo size is changed is the simplest solution. Signed-off-by: Rob Herring Reviewed-by: Peter Maydell Message-id: 1395166721-15716-2-git-send-email-robherring2@gmail.com Signed-off-by: Peter Maydell --- hw/char/pl011.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'hw/char/pl011.c') diff --git a/hw/char/pl011.c b/hw/char/pl011.c index a8ae6f4706..8103e2eeb0 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -162,6 +162,11 @@ static void pl011_write(void *opaque, hwaddr offset, s->fbrd = value; break; case 11: /* UARTLCR_H */ + /* Reset the FIFO state on FIFO enable or disable */ + if ((s->lcr ^ value) & 0x10) { + s->read_count = 0; + s->read_pos = 0; + } s->lcr = value; pl011_set_read_trigger(s); break; -- cgit v1.2.1