From bc72ad67543f5c5d39c005ff0ca72da37642a1fb Mon Sep 17 00:00:00 2001 From: Alex Bligh Date: Wed, 21 Aug 2013 16:03:08 +0100 Subject: aio / timers: Switch entire codebase to the new timer API This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh Signed-off-by: Stefan Hajnoczi --- hw/char/cadence_uart.c | 12 ++++++------ hw/char/serial.c | 22 +++++++++++----------- hw/char/virtio-serial-bus.c | 10 +++++----- 3 files changed, 22 insertions(+), 22 deletions(-) (limited to 'hw/char') diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 3c2e96097b..f8ccbdd13a 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -141,9 +141,9 @@ static void fifo_trigger_update(void *opaque) static void uart_tx_redo(UartState *s) { - uint64_t new_tx_time = qemu_get_clock_ns(vm_clock); + uint64_t new_tx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - qemu_mod_timer(s->tx_time_handle, new_tx_time + s->char_tx_time); + timer_mod(s->tx_time_handle, new_tx_time + s->char_tx_time); s->r[R_SR] |= UART_SR_INTR_TEMPTY; @@ -265,7 +265,7 @@ static void uart_ctrl_update(UartState *s) static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) { UartState *s = (UartState *)opaque; - uint64_t new_rx_time = qemu_get_clock_ns(vm_clock); + uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); int i; if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) { @@ -291,7 +291,7 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) s->r[R_SR] |= UART_SR_INTR_RTRIG; } } - qemu_mod_timer(s->fifo_trigger_handle, new_rx_time + + timer_mod(s->fifo_trigger_handle, new_rx_time + (s->char_tx_time * 4)); } uart_update_status(s); @@ -452,10 +452,10 @@ static int cadence_uart_init(SysBusDevice *dev) sysbus_init_mmio(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); - s->fifo_trigger_handle = qemu_new_timer_ns(vm_clock, + s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *)fifo_trigger_update, s); - s->tx_time_handle = qemu_new_timer_ns(vm_clock, + s->tx_time_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *)uart_tx_write, s); s->char_tx_time = (get_ticks_per_sec() / 9600) * 10; diff --git a/hw/char/serial.c b/hw/char/serial.c index 602559254e..397802081d 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -188,7 +188,7 @@ static void serial_update_msl(SerialState *s) uint8_t omsr; int flags; - qemu_del_timer(s->modem_status_poll); + timer_del(s->modem_status_poll); if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { s->poll_msl = -1; @@ -215,7 +215,7 @@ static void serial_update_msl(SerialState *s) We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ if (s->poll_msl) - qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100); + timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 100); } static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) @@ -252,7 +252,7 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) s->tsr_retry = 0; } - s->last_xmit_ts = qemu_get_clock_ns(vm_clock); + s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); if (s->lsr & UART_LSR_THRE) { s->lsr |= UART_LSR_TEMT; @@ -306,7 +306,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, s->poll_msl = 1; serial_update_msl(s); } else { - qemu_del_timer(s->modem_status_poll); + timer_del(s->modem_status_poll); s->poll_msl = 0; } } @@ -329,7 +329,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, /* FIFO clear */ if (val & UART_FCR_RFR) { - qemu_del_timer(s->fifo_timeout_timer); + timer_del(s->fifo_timeout_timer); s->timeout_ipending=0; fifo8_reset(&s->recv_fifo); } @@ -397,7 +397,7 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); /* Update the modem status after a one-character-send wait-time, since there may be a response from the device/computer at the other end of the serial line */ - qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time); + timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); } } break; @@ -429,7 +429,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) if (s->recv_fifo.num == 0) { s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); } else { - qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); + timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); } s->timeout_ipending = 0; } else { @@ -556,7 +556,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) } s->lsr |= UART_LSR_DR; /* call the timeout receive callback in 4 char transmit time */ - qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); + timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); } else { if (s->lsr & UART_LSR_DR) s->lsr |= UART_LSR_OE; @@ -635,7 +635,7 @@ static void serial_reset(void *opaque) fifo8_reset(&s->recv_fifo); fifo8_reset(&s->xmit_fifo); - s->last_xmit_ts = qemu_get_clock_ns(vm_clock); + s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); s->thr_ipending = 0; s->last_break_enable = 0; @@ -649,9 +649,9 @@ void serial_realize_core(SerialState *s, Error **errp) return; } - s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s); + s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); - s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); + s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); qemu_register_reset(serial_reset, s); qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index da417c7010..f23f555dde 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -603,7 +603,7 @@ static void virtio_serial_post_load_timer_cb(void *opaque) } } g_free(s->post_load->connected); - qemu_free_timer(s->post_load->timer); + timer_free(s->post_load->timer); g_free(s->post_load); s->post_load = NULL; } @@ -618,7 +618,7 @@ static int fetch_active_ports_list(QEMUFile *f, int version_id, s->post_load->connected = g_malloc0(sizeof(*s->post_load->connected) * nr_active_ports); - s->post_load->timer = qemu_new_timer_ns(vm_clock, + s->post_load->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, virtio_serial_post_load_timer_cb, s); @@ -660,7 +660,7 @@ static int fetch_active_ports_list(QEMUFile *f, int version_id, } } } - qemu_mod_timer(s->post_load->timer, 1); + timer_mod(s->post_load->timer, 1); return 0; } @@ -999,8 +999,8 @@ static int virtio_serial_device_exit(DeviceState *dev) g_free(vser->ports_map); if (vser->post_load) { g_free(vser->post_load->connected); - qemu_del_timer(vser->post_load->timer); - qemu_free_timer(vser->post_load->timer); + timer_del(vser->post_load->timer); + timer_free(vser->post_load->timer); g_free(vser->post_load); } virtio_cleanup(vdev); -- cgit v1.2.1