From 6327c221fff955ee979559ec85c148963e06d78f Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Tue, 11 Jun 2013 10:58:25 +1000 Subject: intc/xilinx_intc: Don't clear level sens. IRQs without ACK For level sensitive interrupts, ISR bits are cleared when the input pin is lowered. This is incorrect. Only software can clear ISR bits (via IAR or direct write to ISR with !MER(2)). Signed-off-by: Peter Crosthwaite Signed-off-by: Edgar E. Iglesias --- hw/intc/xilinx_intc.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'hw/intc') diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 5df7008e2f..d243a0015f 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -135,13 +135,7 @@ static void irq_handler(void *opaque, int irq, int level) return; } - /* Update source flops. Don't clear unless level triggered. - Edge triggered interrupts only go away when explicitely acked to - the interrupt controller. */ - if (!(p->c_kind_of_intr & (1 << irq)) || level) { - p->regs[R_ISR] &= ~(1 << irq); - p->regs[R_ISR] |= (level << irq); - } + p->regs[R_ISR] |= (level << irq); update_irq(p); } -- cgit v1.2.1