From cbcaf79e3ce1b14084f3e3f4f64365e9bfd70e6a Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Tue, 10 Sep 2013 10:16:02 +0300 Subject: q35: expose mmcfg size as a property Address is already exposed, expose size for symmetry. Reviewed-by: Gerd Hoffmann Tested-by: Gerd Hoffmann Reviewed-by: Igor Mammedov Tested-by: Igor Mammedov Signed-off-by: Michael S. Tsirkin --- hw/pci-host/q35.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'hw/pci-host') diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index e46f286e24..a051b58ba7 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -109,6 +109,16 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, visit_type_uint64(v, &w64.end, name, errp); } +static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); + uint32_t value = e->size; + + visit_type_uint32(v, &value, name, errp); +} + static Property mch_props[] = { DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), @@ -160,6 +170,10 @@ static void q35_host_initfn(Object *obj) q35_host_get_pci_hole64_end, NULL, NULL, NULL, NULL); + object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", + q35_host_get_mmcfg_size, + NULL, NULL, NULL, NULL); + /* Leave enough space for the biggest MCFG BAR */ /* TODO: this matches current bios behaviour, but * it's not a power of two, which means an MTRR -- cgit v1.2.1