From 2133a5f6b8f8941a6a3734c6c1990656553de76c Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 3 Jun 2013 17:17:43 +0100 Subject: xilinx_spips: Fix CTRL register RW bits The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: b7aaad93163ce4af0c428635804ac7b77a567b25.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'hw/ssi') diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ea8a593214..3e9e76c165 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -56,6 +56,7 @@ #define CLK_PH (1 << 2) #define CLK_POL (1 << 1) #define MODE_SEL (1 << 0) +#define R_CONFIG_RSVD (0x7bf40000) /* interrupt mechanism */ #define R_INTR_STATUS (0x04 / 4) @@ -355,7 +356,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); break; case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; @@ -415,7 +416,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = ~(R_CONFIG_RSVD | MAN_START_COM); if (value & MAN_START_COM) { man_start_com = 1; } -- cgit v1.2.1