From bc72ad67543f5c5d39c005ff0ca72da37642a1fb Mon Sep 17 00:00:00 2001 From: Alex Bligh Date: Wed, 21 Aug 2013 16:03:08 +0100 Subject: aio / timers: Switch entire codebase to the new timer API This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh Signed-off-by: Stefan Hajnoczi --- hw/timer/pxa2xx_timer.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'hw/timer/pxa2xx_timer.c') diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c index cdabccdd15..0f546c4121 100644 --- a/hw/timer/pxa2xx_timer.c +++ b/hw/timer/pxa2xx_timer.c @@ -123,7 +123,7 @@ static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) for (i = 0; i < 4; i ++) { new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), get_ticks_per_sec(), s->freq); - qemu_mod_timer(s->timer[i].qtimer, new_qemu); + timer_mod(s->timer[i].qtimer, new_qemu); } } @@ -141,7 +141,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) counter = counters[n]; if (!s->tm4[counter].freq) { - qemu_del_timer(s->tm4[n].tm.qtimer); + timer_del(s->tm4[n].tm.qtimer); return; } @@ -151,7 +151,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm), get_ticks_per_sec(), s->tm4[counter].freq); - qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu); + timer_mod(s->tm4[n].tm.qtimer, new_qemu); } static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, @@ -188,7 +188,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, goto badreg; return s->tm4[tm].tm.value; case OSCR: - return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) - + return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->lastload, s->freq, get_ticks_per_sec()); case OSCR11: tm ++; /* fall through */ @@ -211,7 +211,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { if (s->tm4[tm - 1].freq) s->snapshot = s->tm4[tm - 1].clock + muldiv64( - qemu_get_clock_ns(vm_clock) - + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->tm4[tm - 1].lastload, s->tm4[tm - 1].freq, get_ticks_per_sec()); else @@ -220,7 +220,7 @@ static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset, if (!s->tm4[tm].freq) return s->tm4[tm].clock; - return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) - + return s->tm4[tm].clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec()); case OIER: return s->irq_enabled; @@ -271,7 +271,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, /* fall through */ case OSMR0: s->timer[tm].value = value; - pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock)); + pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; case OSMR11: tm ++; /* fall through */ @@ -291,11 +291,11 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, if (!pxa2xx_timer_has_tm4(s)) goto badreg; s->tm4[tm].tm.value = value; - pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); + pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); break; case OSCR: s->oldclock = s->clock; - s->lastload = qemu_get_clock_ns(vm_clock); + s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); s->clock = value; pxa2xx_timer_update(s, s->lastload); break; @@ -317,7 +317,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, if (!pxa2xx_timer_has_tm4(s)) goto badreg; s->tm4[tm].oldclock = s->tm4[tm].clock; - s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock); + s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); s->tm4[tm].clock = value; pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); break; @@ -351,7 +351,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7]; else { s->tm4[tm].freq = 0; - pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); + pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); } break; case OMCR11: tm ++; @@ -370,7 +370,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr offset, pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; else { s->tm4[tm].freq = 0; - pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm); + pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm); } break; default: @@ -411,7 +411,7 @@ static void pxa2xx_timer_tick4(void *opaque) if (t->control & (1 << 3)) t->clock = 0; if (t->control & (1 << 6)) - pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4); + pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4); if (i->events & 0xff0) qemu_irq_raise(i->irq4); } @@ -422,7 +422,7 @@ static int pxa25x_timer_post_load(void *opaque, int version_id) int64_t now; int i; - now = qemu_get_clock_ns(vm_clock); + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); pxa2xx_timer_update(s, now); if (pxa2xx_timer_has_tm4(s)) @@ -440,7 +440,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev) s->irq_enabled = 0; s->oldclock = 0; s->clock = 0; - s->lastload = qemu_get_clock_ns(vm_clock); + s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); s->reset3 = 0; for (i = 0; i < 4; i ++) { @@ -448,7 +448,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->timer[i].irq); s->timer[i].info = s; s->timer[i].num = i; - s->timer[i].qtimer = qemu_new_timer_ns(vm_clock, + s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pxa2xx_timer_tick, &s->timer[i]); } if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) { @@ -460,7 +460,7 @@ static int pxa2xx_timer_init(SysBusDevice *dev) s->tm4[i].tm.num = i + 4; s->tm4[i].freq = 0; s->tm4[i].control = 0x0; - s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock, + s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pxa2xx_timer_tick4, &s->tm4[i]); } } -- cgit v1.2.1