From f18cd2238d39950f8a532cb2a2ee48a453d2e88f Mon Sep 17 00:00:00 2001 From: aurel32 Date: Mon, 29 Sep 2008 17:21:28 +0000 Subject: target-alpha: convert FP ops to TCG - Convert FP ops to TCG - Fix S format - Implement F and G formats (untested) - Fix MF_FPCR an MT_FPCR - Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT - Fix CPYSN, CPYSE Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-alpha/cpu.h | 2 - target-alpha/exec.h | 3 - target-alpha/helper.c | 6 - target-alpha/helper.h | 67 +++ target-alpha/op.c | 474 --------------------- target-alpha/op_helper.c | 969 ++++++++++++++++++++----------------------- target-alpha/op_helper.h | 59 --- target-alpha/op_helper_mem.h | 40 -- target-alpha/op_mem.h | 27 -- target-alpha/op_template.h | 85 ---- target-alpha/translate.c | 536 ++++++++++++------------ 11 files changed, 786 insertions(+), 1482 deletions(-) delete mode 100644 target-alpha/op_helper_mem.h delete mode 100644 target-alpha/op_template.h (limited to 'target-alpha') diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index a3458a4146..210cc55f94 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -277,8 +277,6 @@ struct CPUAlphaState { */ target_ulong t0, t1; #endif - /* */ - double ft0, ft1, ft2; /* Those resources are used only in Qemu core */ CPU_COMMON diff --git a/target-alpha/exec.h b/target-alpha/exec.h index 574ef13f10..99c6e95d3f 100644 --- a/target-alpha/exec.h +++ b/target-alpha/exec.h @@ -44,9 +44,6 @@ register uint64_t T1 asm(AREG2); #define PARAM(n) ((uint64_t)PARAM##n) #define SPARAM(n) ((int32_t)PARAM##n) -#define FT0 (env->ft0) -#define FT1 (env->ft1) -#define FT2 (env->ft2) #define FP_STATUS (env->fp_status) #if defined (DEBUG_OP) diff --git a/target-alpha/helper.c b/target-alpha/helper.c index e0d06b452a..41f2e0f7d3 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -434,12 +434,6 @@ void cpu_dump_state (CPUState *env, FILE *f, if ((i % 3) == 2) cpu_fprintf(f, "\n"); } - cpu_fprintf(f, "FT " TARGET_FMT_lx " " TARGET_FMT_lx " " TARGET_FMT_lx, - *((uint64_t *)(&env->ft0)), *((uint64_t *)(&env->ft1)), - *((uint64_t *)(&env->ft2))); - cpu_fprintf(f, "\nMEM " TARGET_FMT_lx " %d %d\n", - ldq_raw(0x000000004007df60ULL), - (uint8_t *)(&env->ft0), (uint8_t *)(&env->fir[0])); } void cpu_dump_EA (target_ulong EA) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 4b07f58b15..6126790d6c 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -41,3 +41,70 @@ DEF_HELPER(uint64_t, helper_mskqh, (int64_t, uint64_t)) DEF_HELPER(uint64_t, helper_insqh, (int64_t, uint64_t)) DEF_HELPER(uint64_t, helper_cmpbge, (uint64_t, uint64_t)) + +DEF_HELPER(uint64_t, helper_load_fpcr, (void)) +DEF_HELPER(void, helper_store_fpcr, (uint64_t val)) + +DEF_HELPER(uint32_t, helper_f_to_memory, (uint64_t s)) +DEF_HELPER(uint64_t, helper_memory_to_f, (uint32_t s)) +DEF_HELPER(uint64_t, helper_addf, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_subf, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_mulf, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_divf, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_sqrtf, (uint64_t)) + +DEF_HELPER(uint64_t, helper_g_to_memory, (uint64_t s)) +DEF_HELPER(uint64_t, helper_memory_to_g, (uint64_t s)) +DEF_HELPER(uint64_t, helper_addg, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_subg, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_mulg, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_divg, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_sqrtg, (uint64_t)) + +DEF_HELPER(uint32_t, helper_s_to_memory, (uint64_t s)) +DEF_HELPER(uint64_t, helper_memory_to_s, (uint32_t s)) +DEF_HELPER(uint64_t, helper_adds, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_subs, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_muls, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_divs, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_sqrts, (uint64_t)) + +DEF_HELPER(uint64_t, helper_addt, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_subt, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_mult, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_divt, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_sqrtt, (uint64_t)) + +DEF_HELPER(uint64_t, helper_cmptun, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cmpteq, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cmptle, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cmptlt, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cmpgeq, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cmpgle, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cmpglt, (uint64_t, uint64_t)) + +DEF_HELPER(uint64_t, helper_cmpfeq, (uint64_t)) +DEF_HELPER(uint64_t, helper_cmpfne, (uint64_t)) +DEF_HELPER(uint64_t, helper_cmpflt, (uint64_t)) +DEF_HELPER(uint64_t, helper_cmpfle, (uint64_t)) +DEF_HELPER(uint64_t, helper_cmpfgt, (uint64_t)) +DEF_HELPER(uint64_t, helper_cmpfge, (uint64_t)) + +DEF_HELPER(uint64_t, helper_cpys, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cpysn, (uint64_t, uint64_t)) +DEF_HELPER(uint64_t, helper_cpyse, (uint64_t, uint64_t)) + +DEF_HELPER(uint64_t, helper_cvtts, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtst, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvttq, (uint64_t)) +DEF_HELPER(uint32_t, helper_cvtqs, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtqt, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtqf, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtgf, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtgq, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtqg, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtlq, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtql, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtqlv, (uint64_t)) +DEF_HELPER(uint64_t, helper_cvtqlsv, (uint64_t)) + diff --git a/target-alpha/op.c b/target-alpha/op.c index 2896c1d4a2..cf29eb9ded 100644 --- a/target-alpha/op.c +++ b/target-alpha/op.c @@ -23,105 +23,8 @@ #include "config.h" #include "exec.h" #include "host-utils.h" - #include "op_helper.h" -#define REG 0 -#include "op_template.h" - -#define REG 1 -#include "op_template.h" - -#define REG 2 -#include "op_template.h" - -#define REG 3 -#include "op_template.h" - -#define REG 4 -#include "op_template.h" - -#define REG 5 -#include "op_template.h" - -#define REG 6 -#include "op_template.h" - -#define REG 7 -#include "op_template.h" - -#define REG 8 -#include "op_template.h" - -#define REG 9 -#include "op_template.h" - -#define REG 10 -#include "op_template.h" - -#define REG 11 -#include "op_template.h" - -#define REG 12 -#include "op_template.h" - -#define REG 13 -#include "op_template.h" - -#define REG 14 -#include "op_template.h" - -#define REG 15 -#include "op_template.h" - -#define REG 16 -#include "op_template.h" - -#define REG 17 -#include "op_template.h" - -#define REG 18 -#include "op_template.h" - -#define REG 19 -#include "op_template.h" - -#define REG 20 -#include "op_template.h" - -#define REG 21 -#include "op_template.h" - -#define REG 22 -#include "op_template.h" - -#define REG 23 -#include "op_template.h" - -#define REG 24 -#include "op_template.h" - -#define REG 25 -#include "op_template.h" - -#define REG 26 -#include "op_template.h" - -#define REG 27 -#include "op_template.h" - -#define REG 28 -#include "op_template.h" - -#define REG 29 -#include "op_template.h" - -#define REG 30 -#include "op_template.h" - -#define REG 31 -#include "op_template.h" - /* Debug stuff */ void OPPROTO op_no_op (void) { @@ -148,383 +51,6 @@ void OPPROTO op_no_op (void) #include "op_mem.h" #endif -/* Misc */ -void OPPROTO op_load_fpcr (void) -{ - helper_load_fpcr(); - RETURN(); -} - -void OPPROTO op_store_fpcr (void) -{ - helper_store_fpcr(); - RETURN(); -} - -/* Tests */ -#if 0 // Qemu does not know how to do this... -void OPPROTO op_bcond (void) -{ - if (T0) - env->pc = T1 & ~3; - else - env->pc = PARAM(1); - RETURN(); -} -#else -void OPPROTO op_bcond (void) -{ - if (T0) - env->pc = T1 & ~3; - else - env->pc = ((uint64_t)PARAM(1) << 32) | (uint64_t)PARAM(2); - RETURN(); -} -#endif - -/* IEEE floating point arithmetic */ -/* S floating (single) */ -void OPPROTO op_adds (void) -{ - FT0 = float32_add(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_subs (void) -{ - FT0 = float32_sub(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_muls (void) -{ - FT0 = float32_mul(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_divs (void) -{ - FT0 = float32_div(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_sqrts (void) -{ - helper_sqrts(); - RETURN(); -} - -void OPPROTO op_cpys (void) -{ - helper_cpys(); - RETURN(); -} - -void OPPROTO op_cpysn (void) -{ - helper_cpysn(); - RETURN(); -} - -void OPPROTO op_cpyse (void) -{ - helper_cpyse(); - RETURN(); -} - -void OPPROTO op_itofs (void) -{ - helper_itofs(); - RETURN(); -} - -void OPPROTO op_ftois (void) -{ - helper_ftois(); - RETURN(); -} - -/* T floating (double) */ -void OPPROTO op_addt (void) -{ - FT0 = float64_add(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_subt (void) -{ - FT0 = float64_sub(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_mult (void) -{ - FT0 = float64_mul(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_divt (void) -{ - FT0 = float64_div(FT0, FT1, &FP_STATUS); - RETURN(); -} - -void OPPROTO op_sqrtt (void) -{ - helper_sqrtt(); - RETURN(); -} - -void OPPROTO op_cmptun (void) -{ - helper_cmptun(); - RETURN(); -} - -void OPPROTO op_cmpteq (void) -{ - helper_cmpteq(); - RETURN(); -} - -void OPPROTO op_cmptle (void) -{ - helper_cmptle(); - RETURN(); -} - -void OPPROTO op_cmptlt (void) -{ - helper_cmptlt(); - RETURN(); -} - -void OPPROTO op_itoft (void) -{ - helper_itoft(); - RETURN(); -} - -void OPPROTO op_ftoit (void) -{ - helper_ftoit(); - RETURN(); -} - -/* VAX floating point arithmetic */ -/* F floating */ -void OPPROTO op_addf (void) -{ - helper_addf(); - RETURN(); -} - -void OPPROTO op_subf (void) -{ - helper_subf(); - RETURN(); -} - -void OPPROTO op_mulf (void) -{ - helper_mulf(); - RETURN(); -} - -void OPPROTO op_divf (void) -{ - helper_divf(); - RETURN(); -} - -void OPPROTO op_sqrtf (void) -{ - helper_sqrtf(); - RETURN(); -} - -void OPPROTO op_cmpfeq (void) -{ - helper_cmpfeq(); - RETURN(); -} - -void OPPROTO op_cmpfne (void) -{ - helper_cmpfne(); - RETURN(); -} - -void OPPROTO op_cmpflt (void) -{ - helper_cmpflt(); - RETURN(); -} - -void OPPROTO op_cmpfle (void) -{ - helper_cmpfle(); - RETURN(); -} - -void OPPROTO op_cmpfgt (void) -{ - helper_cmpfgt(); - RETURN(); -} - -void OPPROTO op_cmpfge (void) -{ - helper_cmpfge(); - RETURN(); -} - -void OPPROTO op_itoff (void) -{ - helper_itoff(); - RETURN(); -} - -/* G floating */ -void OPPROTO op_addg (void) -{ - helper_addg(); - RETURN(); -} - -void OPPROTO op_subg (void) -{ - helper_subg(); - RETURN(); -} - -void OPPROTO op_mulg (void) -{ - helper_mulg(); - RETURN(); -} - -void OPPROTO op_divg (void) -{ - helper_divg(); - RETURN(); -} - -void OPPROTO op_sqrtg (void) -{ - helper_sqrtg(); - RETURN(); -} - -void OPPROTO op_cmpgeq (void) -{ - helper_cmpgeq(); - RETURN(); -} - -void OPPROTO op_cmpglt (void) -{ - helper_cmpglt(); - RETURN(); -} - -void OPPROTO op_cmpgle (void) -{ - helper_cmpgle(); - RETURN(); -} - -/* Floating point format conversion */ -void OPPROTO op_cvtst (void) -{ - FT0 = (float)FT0; - RETURN(); -} - -void OPPROTO op_cvtqs (void) -{ - helper_cvtqs(); - RETURN(); -} - -void OPPROTO op_cvtts (void) -{ - FT0 = (float)FT0; - RETURN(); -} - -void OPPROTO op_cvttq (void) -{ - helper_cvttq(); - RETURN(); -} - -void OPPROTO op_cvtqt (void) -{ - helper_cvtqt(); - RETURN(); -} - -void OPPROTO op_cvtqf (void) -{ - helper_cvtqf(); - RETURN(); -} - -void OPPROTO op_cvtgf (void) -{ - helper_cvtgf(); - RETURN(); -} - -void OPPROTO op_cvtgd (void) -{ - helper_cvtgd(); - RETURN(); -} - -void OPPROTO op_cvtgq (void) -{ - helper_cvtgq(); - RETURN(); -} - -void OPPROTO op_cvtqg (void) -{ - helper_cvtqg(); - RETURN(); -} - -void OPPROTO op_cvtdg (void) -{ - helper_cvtdg(); - RETURN(); -} - -void OPPROTO op_cvtlq (void) -{ - helper_cvtlq(); - RETURN(); -} - -void OPPROTO op_cvtql (void) -{ - helper_cvtql(); - RETURN(); -} - -void OPPROTO op_cvtqlv (void) -{ - helper_cvtqlv(); - RETURN(); -} - -void OPPROTO op_cvtqlsv (void) -{ - helper_cvtqlsv(); - RETURN(); -} - /* PALcode support special instructions */ #if !defined (CONFIG_USER_ONLY) void OPPROTO op_hw_rei (void) diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index b8830487ef..bd20d33aab 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -24,27 +24,6 @@ #include "op_helper.h" -#define MEMSUFFIX _raw -#include "op_helper_mem.h" - -#if !defined(CONFIG_USER_ONLY) -#define MEMSUFFIX _kernel -#include "op_helper_mem.h" - -#define MEMSUFFIX _executive -#include "op_helper_mem.h" - -#define MEMSUFFIX _supervisor -#include "op_helper_mem.h" - -#define MEMSUFFIX _user -#include "op_helper_mem.h" - -/* This is used for pal modes */ -#define MEMSUFFIX _data -#include "op_helper_mem.h" -#endif - void helper_tb_flush (void) { tlb_flush(env, 1); @@ -91,37 +70,38 @@ uint64_t helper_load_implver (void) return env->implver; } -void helper_load_fpcr (void) +uint64_t helper_load_fpcr (void) { - T0 = 0; + uint64_t ret = 0; #ifdef CONFIG_SOFTFLOAT - T0 |= env->fp_status.float_exception_flags << 52; + ret |= env->fp_status.float_exception_flags << 52; if (env->fp_status.float_exception_flags) - T0 |= 1ULL << 63; + ret |= 1ULL << 63; env->ipr[IPR_EXC_SUM] &= ~0x3E: env->ipr[IPR_EXC_SUM] |= env->fp_status.float_exception_flags << 1; #endif switch (env->fp_status.float_rounding_mode) { case float_round_nearest_even: - T0 |= 2ULL << 58; + ret |= 2ULL << 58; break; case float_round_down: - T0 |= 1ULL << 58; + ret |= 1ULL << 58; break; case float_round_up: - T0 |= 3ULL << 58; + ret |= 3ULL << 58; break; case float_round_to_zero: break; } + return ret; } -void helper_store_fpcr (void) +void helper_store_fpcr (uint64_t val) { #ifdef CONFIG_SOFTFLOAT - set_float_exception_flags((T0 >> 52) & 0x3F, &FP_STATUS); + set_float_exception_flags((val >> 52) & 0x3F, &FP_STATUS); #endif - switch ((T0 >> 58) & 3) { + switch ((val >> 58) & 3) { case 0: set_float_rounding_mode(float_round_to_zero, &FP_STATUS); break; @@ -367,675 +347,647 @@ uint64_t helper_cmpbge (uint64_t op1, uint64_t op2) return res; } -void helper_cmov_fir (int freg) +/* Floating point helpers */ + +/* F floating (VAX) */ +static always_inline uint64_t float32_to_f (float32 fa) { - if (FT0 != 0) - env->fir[freg] = FT1; + uint32_t a; + uint64_t r, exp, mant, sig; + + a = *(uint32_t*)(&fa); + sig = ((uint64_t)a & 0x80000000) << 32; + exp = (a >> 23) & 0xff; + mant = ((uint64_t)a & 0x007fffff) << 29; + + if (exp == 255) { + /* NaN or infinity */ + r = 1; /* VAX dirty zero */ + } else if (exp == 0) { + if (mant == 0) { + /* Zero */ + r = 0; + } else { + /* Denormalized */ + r = sig | ((exp + 1) << 52) | mant; + } + } else { + if (exp >= 253) { + /* Overflow */ + r = 1; /* VAX dirty zero */ + } else { + r = sig | ((exp + 2) << 52); + } + } + + return r; } -void helper_sqrts (void) +static always_inline float32 f_to_float32 (uint64_t a) { - FT0 = float32_sqrt(FT0, &FP_STATUS); + uint32_t r, exp, mant_sig; + + exp = ((a >> 55) & 0x80) | ((a >> 52) & 0x7f); + mant_sig = ((a >> 32) & 0x80000000) | ((a >> 29) & 0x007fffff); + + if (unlikely(!exp && mant_sig)) { + /* Reserved operands / Dirty zero */ + helper_excp(EXCP_OPCDEC, 0); + } + + if (exp < 3) { + /* Underflow */ + r = 0; + } else { + r = ((exp - 2) << 23) | mant_sig; + } + + return *(float32*)(&a); } -void helper_cpys (void) +uint32_t helper_f_to_memory (uint64_t a) { - union { - double d; - uint64_t i; - } p, q, r; + uint32_t r; + r = (a & 0x00001fffe0000000ull) >> 13; + r |= (a & 0x07ffe00000000000ull) >> 45; + r |= (a & 0xc000000000000000ull) >> 48; + return r; +} - p.d = FT0; - q.d = FT1; - r.i = p.i & 0x8000000000000000ULL; - r.i |= q.i & ~0x8000000000000000ULL; - FT0 = r.d; +uint64_t helper_memory_to_f (uint32_t a) +{ + uint64_t r; + r = ((uint64_t)(a & 0x0000c000)) << 48; + r |= ((uint64_t)(a & 0x003fffff)) << 45; + r |= ((uint64_t)(a & 0xffff0000)) << 13; + if (!(a & 0x00004000)) + r |= 0x7ll << 59; + return r; } -void helper_cpysn (void) +uint64_t helper_addf (uint64_t a, uint64_t b) { - union { - double d; - uint64_t i; - } p, q, r; + float32 fa, fb, fr; - p.d = FT0; - q.d = FT1; - r.i = (~p.i) & 0x8000000000000000ULL; - r.i |= q.i & ~0x8000000000000000ULL; - FT0 = r.d; + fa = f_to_float32(a); + fb = f_to_float32(b); + fr = float32_add(fa, fb, &FP_STATUS); + return float32_to_f(fr); } -void helper_cpyse (void) +uint64_t helper_subf (uint64_t a, uint64_t b) { - union { - double d; - uint64_t i; - } p, q, r; + float32 fa, fb, fr; - p.d = FT0; - q.d = FT1; - r.i = p.i & 0xFFF0000000000000ULL; - r.i |= q.i & ~0xFFF0000000000000ULL; - FT0 = r.d; + fa = f_to_float32(a); + fb = f_to_float32(b); + fr = float32_sub(fa, fb, &FP_STATUS); + return float32_to_f(fr); } -void helper_itofs (void) +uint64_t helper_mulf (uint64_t a, uint64_t b) { - union { - double d; - uint64_t i; - } p; + float32 fa, fb, fr; - p.d = FT0; - FT0 = int64_to_float32(p.i, &FP_STATUS); + fa = f_to_float32(a); + fb = f_to_float32(b); + fr = float32_mul(fa, fb, &FP_STATUS); + return float32_to_f(fr); } -void helper_ftois (void) +uint64_t helper_divf (uint64_t a, uint64_t b) { - union { - double d; - uint64_t i; - } p; + float32 fa, fb, fr; - p.i = float32_to_int64(FT0, &FP_STATUS); - FT0 = p.d; + fa = f_to_float32(a); + fb = f_to_float32(b); + fr = float32_div(fa, fb, &FP_STATUS); + return float32_to_f(fr); } -void helper_sqrtt (void) +uint64_t helper_sqrtf (uint64_t t) { - FT0 = float64_sqrt(FT0, &FP_STATUS); + float32 ft, fr; + + ft = f_to_float32(t); + fr = float32_sqrt(ft, &FP_STATUS); + return float32_to_f(fr); } -void helper_cmptun (void) + +/* G floating (VAX) */ +static always_inline uint64_t float64_to_g (float64 fa) { - union { - double d; - uint64_t i; - } p; + uint64_t a, r, exp, mant, sig; - p.i = 0; - if (float64_is_nan(FT0) || float64_is_nan(FT1)) - p.i = 0x4000000000000000ULL; - FT0 = p.d; + a = *(uint64_t*)(&fa); + sig = a & 0x8000000000000000ull; + exp = (a >> 52) & 0x7ff; + mant = a & 0x000fffffffffffffull; + + if (exp == 2047) { + /* NaN or infinity */ + r = 1; /* VAX dirty zero */ + } else if (exp == 0) { + if (mant == 0) { + /* Zero */ + r = 0; + } else { + /* Denormalized */ + r = sig | ((exp + 1) << 52) | mant; + } + } else { + if (exp >= 2045) { + /* Overflow */ + r = 1; /* VAX dirty zero */ + } else { + r = sig | ((exp + 2) << 52); + } + } + + return r; } -void helper_cmpteq (void) +static always_inline float64 g_to_float64 (uint64_t a) { - union { - double d; - uint64_t i; - } p; + uint64_t r, exp, mant_sig; + + exp = (a >> 52) & 0x7ff; + mant_sig = a & 0x800fffffffffffffull; + + if (!exp && mant_sig) { + /* Reserved operands / Dirty zero */ + helper_excp(EXCP_OPCDEC, 0); + } - p.i = 0; - if (float64_eq(FT0, FT1, &FP_STATUS)) - p.i = 0x4000000000000000ULL; - FT0 = p.d; + if (exp < 3) { + /* Underflow */ + r = 0; + } else { + r = ((exp - 2) << 52) | mant_sig; + } + + return *(float64*)(&a); } -void helper_cmptle (void) +uint64_t helper_g_to_memory (uint64_t a) { - union { - double d; - uint64_t i; - } p; + uint64_t r; + r = (a & 0x000000000000ffffull) << 48; + r |= (a & 0x00000000ffff0000ull) << 16; + r |= (a & 0x0000ffff00000000ull) >> 16; + r |= (a & 0xffff000000000000ull) >> 48; + return r; +} - p.i = 0; - if (float64_le(FT0, FT1, &FP_STATUS)) - p.i = 0x4000000000000000ULL; - FT0 = p.d; +uint64_t helper_memory_to_g (uint64_t a) +{ + uint64_t r; + r = (a & 0x000000000000ffffull) << 48; + r |= (a & 0x00000000ffff0000ull) << 16; + r |= (a & 0x0000ffff00000000ull) >> 16; + r |= (a & 0xffff000000000000ull) >> 48; + return r; } -void helper_cmptlt (void) +uint64_t helper_addg (uint64_t a, uint64_t b) { - union { - double d; - uint64_t i; - } p; + float64 fa, fb, fr; - p.i = 0; - if (float64_lt(FT0, FT1, &FP_STATUS)) - p.i = 0x4000000000000000ULL; - FT0 = p.d; + fa = g_to_float64(a); + fb = g_to_float64(b); + fr = float64_add(fa, fb, &FP_STATUS); + return float64_to_g(fr); } -void helper_itoft (void) +uint64_t helper_subg (uint64_t a, uint64_t b) { - union { - double d; - uint64_t i; - } p; + float64 fa, fb, fr; - p.d = FT0; - FT0 = int64_to_float64(p.i, &FP_STATUS); + fa = g_to_float64(a); + fb = g_to_float64(b); + fr = float64_sub(fa, fb, &FP_STATUS); + return float64_to_g(fr); } -void helper_ftoit (void) +uint64_t helper_mulg (uint64_t a, uint64_t b) { - union { - double d; - uint64_t i; - } p; + float64 fa, fb, fr; - p.i = float64_to_int64(FT0, &FP_STATUS); - FT0 = p.d; + fa = g_to_float64(a); + fb = g_to_float64(b); + fr = float64_mul(fa, fb, &FP_STATUS); + return float64_to_g(fr); } -static always_inline int vaxf_is_valid (float ff) +uint64_t helper_divg (uint64_t a, uint64_t b) { - union { - float f; - uint32_t i; - } p; - uint32_t exp, mant; + float64 fa, fb, fr; - p.f = ff; - exp = (p.i >> 23) & 0xFF; - mant = p.i & 0x007FFFFF; - if (exp == 0 && ((p.i & 0x80000000) || mant != 0)) { - /* Reserved operands / Dirty zero */ - return 0; - } + fa = g_to_float64(a); + fb = g_to_float64(b); + fr = float64_div(fa, fb, &FP_STATUS); + return float64_to_g(fr); +} + +uint64_t helper_sqrtg (uint64_t a) +{ + float64 fa, fr; - return 1; + fa = g_to_float64(a); + fr = float64_sqrt(fa, &FP_STATUS); + return float64_to_g(fr); } -static always_inline float vaxf_to_ieee32 (float ff) + +/* S floating (single) */ +static always_inline uint64_t float32_to_s (float32 fa) { - union { - float f; - uint32_t i; - } p; - uint32_t exp; + uint32_t a; + uint64_t r; - p.f = ff; - exp = (p.i >> 23) & 0xFF; - if (exp < 3) { - /* Underflow */ - p.f = 0.0; - } else { - p.f *= 0.25; - } + a = *(uint32_t*)(&fa); - return p.f; + r = (((uint64_t)(a & 0xc0000000)) << 32) | (((uint64_t)(a & 0x3fffffff)) << 29); + if (((a & 0x7f800000) != 0x7f800000) && (!(a & 0x40000000))) + r |= 0x7ll << 59; + return r; } -static always_inline float ieee32_to_vaxf (float fi) +static always_inline float32 s_to_float32 (uint64_t a) { - union { - float f; - uint32_t i; - } p; - uint32_t exp, mant; + uint32_t r = ((a >> 32) & 0xc0000000) | ((a >> 29) & 0x3fffffff); + return *(float32*)(&r); +} - p.f = fi; - exp = (p.i >> 23) & 0xFF; - mant = p.i & 0x007FFFFF; - if (exp == 255) { - /* NaN or infinity */ - p.i = 1; - } else if (exp == 0) { - if (mant == 0) { - /* Zero */ - p.i = 0; - } else { - /* Denormalized */ - p.f *= 2.0; - } - } else { - if (exp >= 253) { - /* Overflow */ - p.i = 1; - } else { - p.f *= 4.0; - } - } +uint32_t helper_s_to_memory (uint64_t a) +{ + /* Memory format is the same as float32 */ + float32 fa = s_to_float32(a); + return *(uint32_t*)(&fa); +} - return p.f; +uint64_t helper_memory_to_s (uint32_t a) +{ + /* Memory format is the same as float32 */ + return float32_to_s(*(float32*)(&a)); } -void helper_addf (void) +uint64_t helper_adds (uint64_t a, uint64_t b) { - float ft0, ft1, ft2; + float32 fa, fb, fr; - if (!vaxf_is_valid(FT0) || !vaxf_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxf_to_ieee32(FT0); - ft1 = vaxf_to_ieee32(FT1); - ft2 = float32_add(ft0, ft1, &FP_STATUS); - FT0 = ieee32_to_vaxf(ft2); + fa = s_to_float32(a); + fb = s_to_float32(b); + fr = float32_add(fa, fb, &FP_STATUS); + return float32_to_s(fr); } -void helper_subf (void) +uint64_t helper_subs (uint64_t a, uint64_t b) { - float ft0, ft1, ft2; + float32 fa, fb, fr; - if (!vaxf_is_valid(FT0) || !vaxf_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxf_to_ieee32(FT0); - ft1 = vaxf_to_ieee32(FT1); - ft2 = float32_sub(ft0, ft1, &FP_STATUS); - FT0 = ieee32_to_vaxf(ft2); + fa = s_to_float32(a); + fb = s_to_float32(b); + fr = float32_sub(fa, fb, &FP_STATUS); + return float32_to_s(fr); } -void helper_mulf (void) +uint64_t helper_muls (uint64_t a, uint64_t b) { - float ft0, ft1, ft2; + float32 fa, fb, fr; - if (!vaxf_is_valid(FT0) || !vaxf_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxf_to_ieee32(FT0); - ft1 = vaxf_to_ieee32(FT1); - ft2 = float32_mul(ft0, ft1, &FP_STATUS); - FT0 = ieee32_to_vaxf(ft2); + fa = s_to_float32(a); + fb = s_to_float32(b); + fr = float32_mul(fa, fb, &FP_STATUS); + return float32_to_s(fr); } -void helper_divf (void) +uint64_t helper_divs (uint64_t a, uint64_t b) { - float ft0, ft1, ft2; + float32 fa, fb, fr; - if (!vaxf_is_valid(FT0) || !vaxf_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxf_to_ieee32(FT0); - ft1 = vaxf_to_ieee32(FT1); - ft2 = float32_div(ft0, ft1, &FP_STATUS); - FT0 = ieee32_to_vaxf(ft2); + fa = s_to_float32(a); + fb = s_to_float32(b); + fr = float32_div(fa, fb, &FP_STATUS); + return float32_to_s(fr); } -void helper_sqrtf (void) +uint64_t helper_sqrts (uint64_t a) { - float ft0, ft1; + float32 fa, fr; - if (!vaxf_is_valid(FT0) || !vaxf_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxf_to_ieee32(FT0); - ft1 = float32_sqrt(ft0, &FP_STATUS); - FT0 = ieee32_to_vaxf(ft1); + fa = s_to_float32(a); + fr = float32_sqrt(fa, &FP_STATUS); + return float32_to_s(fr); } -void helper_itoff (void) + +/* T floating (double) */ +static always_inline float64 t_to_float64 (uint64_t a) { - /* XXX: TODO */ + /* Memory format is the same as float64 */ + return *(float64*)(&a); } -static always_inline int vaxg_is_valid (double ff) +static always_inline uint64_t float64_to_t (float64 fa) { - union { - double f; - uint64_t i; - } p; - uint64_t exp, mant; + /* Memory format is the same as float64 */ + return *(uint64*)(&fa); +} - p.f = ff; - exp = (p.i >> 52) & 0x7FF; - mant = p.i & 0x000FFFFFFFFFFFFFULL; - if (exp == 0 && ((p.i & 0x8000000000000000ULL) || mant != 0)) { - /* Reserved operands / Dirty zero */ - return 0; - } +uint64_t helper_addt (uint64_t a, uint64_t b) +{ + float64 fa, fb, fr; - return 1; + fa = t_to_float64(a); + fb = t_to_float64(b); + fr = float64_add(fa, fb, &FP_STATUS); + return float64_to_t(fr); } -static always_inline double vaxg_to_ieee64 (double fg) +uint64_t helper_subt (uint64_t a, uint64_t b) { - union { - double f; - uint64_t i; - } p; - uint32_t exp; + float64 fa, fb, fr; - p.f = fg; - exp = (p.i >> 52) & 0x7FF; - if (exp < 3) { - /* Underflow */ - p.f = 0.0; - } else { - p.f *= 0.25; - } - - return p.f; + fa = t_to_float64(a); + fb = t_to_float64(b); + fr = float64_sub(fa, fb, &FP_STATUS); + return float64_to_t(fr); } -static always_inline double ieee64_to_vaxg (double fi) +uint64_t helper_mult (uint64_t a, uint64_t b) { - union { - double f; - uint64_t i; - } p; - uint64_t mant; - uint32_t exp; - - p.f = fi; - exp = (p.i >> 52) & 0x7FF; - mant = p.i & 0x000FFFFFFFFFFFFFULL; - if (exp == 255) { - /* NaN or infinity */ - p.i = 1; /* VAX dirty zero */ - } else if (exp == 0) { - if (mant == 0) { - /* Zero */ - p.i = 0; - } else { - /* Denormalized */ - p.f *= 2.0; - } - } else { - if (exp >= 2045) { - /* Overflow */ - p.i = 1; /* VAX dirty zero */ - } else { - p.f *= 4.0; - } - } + float64 fa, fb, fr; - return p.f; + fa = t_to_float64(a); + fb = t_to_float64(b); + fr = float64_mul(fa, fb, &FP_STATUS); + return float64_to_t(fr); } -void helper_addg (void) +uint64_t helper_divt (uint64_t a, uint64_t b) { - double ft0, ft1, ft2; + float64 fa, fb, fr; - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = vaxg_to_ieee64(FT1); - ft2 = float64_add(ft0, ft1, &FP_STATUS); - FT0 = ieee64_to_vaxg(ft2); + fa = t_to_float64(a); + fb = t_to_float64(b); + fr = float64_div(fa, fb, &FP_STATUS); + return float64_to_t(fr); } -void helper_subg (void) +uint64_t helper_sqrtt (uint64_t a) { - double ft0, ft1, ft2; + float64 fa, fr; - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = vaxg_to_ieee64(FT1); - ft2 = float64_sub(ft0, ft1, &FP_STATUS); - FT0 = ieee64_to_vaxg(ft2); + fa = t_to_float64(a); + fr = float64_sqrt(fa, &FP_STATUS); + return float64_to_t(fr); } -void helper_mulg (void) -{ - double ft0, ft1, ft2; - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = vaxg_to_ieee64(FT1); - ft2 = float64_mul(ft0, ft1, &FP_STATUS); - FT0 = ieee64_to_vaxg(ft2); +/* Sign copy */ +uint64_t helper_cpys(uint64_t a, uint64_t b) +{ + return (a & 0x8000000000000000ULL) | (b & ~0x8000000000000000ULL); } -void helper_divg (void) +uint64_t helper_cpysn(uint64_t a, uint64_t b) { - double ft0, ft1, ft2; + return ((~a) & 0x8000000000000000ULL) | (b & ~0x8000000000000000ULL); +} - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = vaxg_to_ieee64(FT1); - ft2 = float64_div(ft0, ft1, &FP_STATUS); - FT0 = ieee64_to_vaxg(ft2); +uint64_t helper_cpyse(uint64_t a, uint64_t b) +{ + return (a & 0xFFF0000000000000ULL) | (b & ~0xFFF0000000000000ULL); } -void helper_sqrtg (void) + +/* Comparisons */ +uint64_t helper_cmptun (uint64_t a, uint64_t b) { - double ft0, ft1; + float64 fa, fb; - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = float64_sqrt(ft0, &FP_STATUS); - FT0 = ieee64_to_vaxg(ft1); + fa = t_to_float64(a); + fb = t_to_float64(b); + + if (float64_is_nan(fa) || float64_is_nan(fb)) + return 0x4000000000000000ULL; + else + return 0; } -void helper_cmpgeq (void) +uint64_t helper_cmpteq(uint64_t a, uint64_t b) { - union { - double d; - uint64_t u; - } p; - double ft0, ft1; + float64 fa, fb; - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = vaxg_to_ieee64(FT1); - p.u = 0; - if (float64_eq(ft0, ft1, &FP_STATUS)) - p.u = 0x4000000000000000ULL; - FT0 = p.d; + fa = t_to_float64(a); + fb = t_to_float64(b); + + if (float64_eq(fa, fb, &FP_STATUS)) + return 0x4000000000000000ULL; + else + return 0; } -void helper_cmpglt (void) +uint64_t helper_cmptle(uint64_t a, uint64_t b) { - union { - double d; - uint64_t u; - } p; - double ft0, ft1; + float64 fa, fb; - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = vaxg_to_ieee64(FT1); - p.u = 0; - if (float64_lt(ft0, ft1, &FP_STATUS)) - p.u = 0x4000000000000000ULL; - FT0 = p.d; + fa = t_to_float64(a); + fb = t_to_float64(b); + + if (float64_le(fa, fb, &FP_STATUS)) + return 0x4000000000000000ULL; + else + return 0; } -void helper_cmpgle (void) +uint64_t helper_cmptlt(uint64_t a, uint64_t b) { - union { - double d; - uint64_t u; - } p; - double ft0, ft1; + float64 fa, fb; - if (!vaxg_is_valid(FT0) || !vaxg_is_valid(FT1)) { - /* XXX: TODO */ - } - ft0 = vaxg_to_ieee64(FT0); - ft1 = vaxg_to_ieee64(FT1); - p.u = 0; - if (float64_le(ft0, ft1, &FP_STATUS)) - p.u = 0x4000000000000000ULL; - FT0 = p.d; + fa = t_to_float64(a); + fb = t_to_float64(b); + + if (float64_lt(fa, fb, &FP_STATUS)) + return 0x4000000000000000ULL; + else + return 0; } -void helper_cvtqs (void) +uint64_t helper_cmpgeq(uint64_t a, uint64_t b) { - union { - double d; - uint64_t u; - } p; + float64 fa, fb; - p.d = FT0; - FT0 = (float)p.u; + fa = g_to_float64(a); + fb = g_to_float64(b); + + if (float64_eq(fa, fb, &FP_STATUS)) + return 0x4000000000000000ULL; + else + return 0; } -void helper_cvttq (void) +uint64_t helper_cmpgle(uint64_t a, uint64_t b) { - union { - double d; - uint64_t u; - } p; + float64 fa, fb; + + fa = g_to_float64(a); + fb = g_to_float64(b); - p.u = FT0; - FT0 = p.d; + if (float64_le(fa, fb, &FP_STATUS)) + return 0x4000000000000000ULL; + else + return 0; } -void helper_cvtqt (void) +uint64_t helper_cmpglt(uint64_t a, uint64_t b) { - union { - double d; - uint64_t u; - } p; + float64 fa, fb; + + fa = g_to_float64(a); + fb = g_to_float64(b); - p.d = FT0; - FT0 = p.u; + if (float64_lt(fa, fb, &FP_STATUS)) + return 0x4000000000000000ULL; + else + return 0; } -void helper_cvtqf (void) +uint64_t helper_cmpfeq (uint64_t a) { - union { - double d; - uint64_t u; - } p; - - p.d = FT0; - FT0 = ieee32_to_vaxf(p.u); + return !(a & 0x7FFFFFFFFFFFFFFFULL); } -void helper_cvtgf (void) +uint64_t helper_cmpfne (uint64_t a) { - double ft0; + return (a & 0x7FFFFFFFFFFFFFFFULL); +} - ft0 = vaxg_to_ieee64(FT0); - FT0 = ieee32_to_vaxf(ft0); +uint64_t helper_cmpflt (uint64_t a) +{ + return (a & 0x8000000000000000ULL) && (a & 0x7FFFFFFFFFFFFFFFULL); } -void helper_cvtgd (void) +uint64_t helper_cmpfle (uint64_t a) { - /* XXX: TODO */ + return (a & 0x8000000000000000ULL) || !(a & 0x7FFFFFFFFFFFFFFFULL); } -void helper_cvtgq (void) +uint64_t helper_cmpfgt (uint64_t a) { - union { - double d; - uint64_t u; - } p; + return !(a & 0x8000000000000000ULL) && (a & 0x7FFFFFFFFFFFFFFFULL); +} - p.u = vaxg_to_ieee64(FT0); - FT0 = p.d; +uint64_t helper_cmpfge (uint64_t a) +{ + return !(a & 0x8000000000000000ULL) || !(a & 0x7FFFFFFFFFFFFFFFULL); } -void helper_cvtqg (void) + +/* Floating point format conversion */ +uint64_t helper_cvtts (uint64_t a) { - union { - double d; - uint64_t u; - } p; + float64 fa; + float32 fr; - p.d = FT0; - FT0 = ieee64_to_vaxg(p.u); + fa = t_to_float64(a); + fr = float64_to_float32(fa, &FP_STATUS); + return float32_to_s(fr); } -void helper_cvtdg (void) +uint64_t helper_cvtst (uint64_t a) { - /* XXX: TODO */ + float32 fa; + float64 fr; + + fa = s_to_float32(a); + fr = float32_to_float64(fa, &FP_STATUS); + return float64_to_t(fr); } -void helper_cvtlq (void) +uint64_t helper_cvtqs (uint64_t a) { - union { - double d; - uint64_t u; - } p, q; - - p.d = FT0; - q.u = (p.u >> 29) & 0x3FFFFFFF; - q.u |= (p.u >> 32); - q.u = (int64_t)((int32_t)q.u); - FT0 = q.d; + float32 fr = int64_to_float32(a, &FP_STATUS); + return float32_to_s(fr); } -static always_inline void __helper_cvtql (int s, int v) +uint64_t helper_cvttq (uint64_t a) { - union { - double d; - uint64_t u; - } p, q; + float64 fa = t_to_float64(a); + return float64_to_int64_round_to_zero(fa, &FP_STATUS); +} - p.d = FT0; - q.u = ((uint64_t)(p.u & 0xC0000000)) << 32; - q.u |= ((uint64_t)(p.u & 0x7FFFFFFF)) << 29; - FT0 = q.d; - if (v && (int64_t)((int32_t)p.u) != (int64_t)p.u) { - helper_excp(EXCP_ARITH, EXCP_ARITH_OVERFLOW); - } - if (s) { - /* TODO */ - } +uint64_t helper_cvtqt (uint64_t a) +{ + float64 fr = int64_to_float64(a, &FP_STATUS); + return float64_to_t(fr); } -void helper_cvtql (void) +uint64_t helper_cvtqf (uint64_t a) { - __helper_cvtql(0, 0); + float32 fr = int64_to_float32(a, &FP_STATUS); + return float32_to_f(fr); } -void helper_cvtqlv (void) +uint64_t helper_cvtgf (uint64_t a) { - __helper_cvtql(0, 1); + float64 fa; + float32 fr; + + fa = g_to_float64(a); + fr = float64_to_float32(fa, &FP_STATUS); + return float32_to_f(fr); } -void helper_cvtqlsv (void) +uint64_t helper_cvtgq (uint64_t a) { - __helper_cvtql(1, 1); + float64 fa = g_to_float64(a); + return float64_to_int64_round_to_zero(fa, &FP_STATUS); } -void helper_cmpfeq (void) +uint64_t helper_cvtqg (uint64_t a) { - if (float64_eq(FT0, FT1, &FP_STATUS)) - T0 = 1; - else - T0 = 0; + float64 fr; + fr = int64_to_float64(a, &FP_STATUS); + return float64_to_g(fr); } -void helper_cmpfne (void) +uint64_t helper_cvtlq (uint64_t a) { - if (float64_eq(FT0, FT1, &FP_STATUS)) - T0 = 0; - else - T0 = 1; + return (int64_t)((int32_t)((a >> 32) | ((a >> 29) & 0x3FFFFFFF))); } -void helper_cmpflt (void) +static always_inline uint64_t __helper_cvtql (uint64_t a, int s, int v) { - if (float64_lt(FT0, FT1, &FP_STATUS)) - T0 = 1; - else - T0 = 0; + uint64_t r; + + r = ((uint64_t)(a & 0xC0000000)) << 32; + r |= ((uint64_t)(a & 0x7FFFFFFF)) << 29; + + if (v && (int64_t)((int32_t)r) != (int64_t)r) { + helper_excp(EXCP_ARITH, EXCP_ARITH_OVERFLOW); + } + if (s) { + /* TODO */ + } + return r; } -void helper_cmpfle (void) +uint64_t helper_cvtql (uint64_t a) { - if (float64_lt(FT0, FT1, &FP_STATUS)) - T0 = 1; - else - T0 = 0; + return __helper_cvtql(a, 0, 0); } -void helper_cmpfgt (void) +uint64_t helper_cvtqlv (uint64_t a) { - if (float64_le(FT0, FT1, &FP_STATUS)) - T0 = 0; - else - T0 = 1; + return __helper_cvtql(a, 0, 1); } -void helper_cmpfge (void) +uint64_t helper_cvtqlsv (uint64_t a) { - if (float64_lt(FT0, FT1, &FP_STATUS)) - T0 = 0; - else - T0 = 1; + return __helper_cvtql(a, 1, 1); } #if !defined (CONFIG_USER_ONLY) @@ -1053,23 +1005,6 @@ void helper_mtpr (int iprn) } #endif -#if defined(HOST_SPARC) || defined(HOST_SPARC64) -void helper_reset_FT0 (void) -{ - FT0 = 0; -} - -void helper_reset_FT1 (void) -{ - FT1 = 0; -} - -void helper_reset_FT2 (void) -{ - FT2 = 0; -} -#endif - /*****************************************************************************/ /* Softmmu support */ #if !defined (CONFIG_USER_ONLY) diff --git a/target-alpha/op_helper.h b/target-alpha/op_helper.h index bcc488e247..2afe16fc53 100644 --- a/target-alpha/op_helper.h +++ b/target-alpha/op_helper.h @@ -19,9 +19,6 @@ */ void helper_call_pal (uint32_t palcode); -void helper_load_fpcr (void); -void helper_store_fpcr (void); -void helper_cmov_fir (int freg); double helper_ldff_raw (target_ulong ea); void helper_stff_raw (target_ulong ea, double op); @@ -42,65 +39,9 @@ double helper_ldfg_data (target_ulong ea); void helper_stfg_data (target_ulong ea, double op); #endif -void helper_sqrts (void); -void helper_cpys (void); -void helper_cpysn (void); -void helper_cpyse (void); -void helper_itofs (void); -void helper_ftois (void); - -void helper_sqrtt (void); -void helper_cmptun (void); -void helper_cmpteq (void); -void helper_cmptle (void); -void helper_cmptlt (void); -void helper_itoft (void); -void helper_ftoit (void); - -void helper_addf (void); -void helper_subf (void); -void helper_mulf (void); -void helper_divf (void); -void helper_sqrtf (void); -void helper_cmpfeq (void); -void helper_cmpfne (void); -void helper_cmpflt (void); -void helper_cmpfle (void); -void helper_cmpfgt (void); -void helper_cmpfge (void); -void helper_itoff (void); - -void helper_addg (void); -void helper_subg (void); -void helper_mulg (void); -void helper_divg (void); -void helper_sqrtg (void); -void helper_cmpgeq (void); -void helper_cmpglt (void); -void helper_cmpgle (void); - -void helper_cvtqs (void); -void helper_cvttq (void); -void helper_cvtqt (void); -void helper_cvtqf (void); -void helper_cvtgf (void); -void helper_cvtgd (void); -void helper_cvtgq (void); -void helper_cvtqg (void); -void helper_cvtdg (void); -void helper_cvtlq (void); -void helper_cvtql (void); -void helper_cvtqlv (void); -void helper_cvtqlsv (void); - void helper_mfpr (int iprn); void helper_mtpr (int iprn); void helper_ld_phys_to_virt (void); void helper_st_phys_to_virt (void); void helper_tb_flush (void); -#if defined(HOST_SPARC) || defined(HOST_SPARC64) -void helper_reset_FT0 (void); -void helper_reset_FT1 (void); -void helper_reset_FT2 (void); -#endif diff --git a/target-alpha/op_helper_mem.h b/target-alpha/op_helper_mem.h deleted file mode 100644 index 09c39bb80a..0000000000 --- a/target-alpha/op_helper_mem.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Alpha emulation cpu micro-operations helpers for memory accesses for qemu. - * - * Copyright (c) 2007 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* XXX: TODO */ -double glue(helper_ldff, MEMSUFFIX) (target_ulong ea) -{ - return 0; -} - -void glue(helper_stff, MEMSUFFIX) (target_ulong ea, double op) -{ -} - -double glue(helper_ldfg, MEMSUFFIX) (target_ulong ea) -{ - return 0; -} - -void glue(helper_stfg, MEMSUFFIX) (target_ulong ea, double op) -{ -} - -#undef MEMSUFFIX diff --git a/target-alpha/op_mem.h b/target-alpha/op_mem.h index 63e59a64ab..0d031a28c5 100644 --- a/target-alpha/op_mem.h +++ b/target-alpha/op_mem.h @@ -90,31 +90,4 @@ ALPHA_LD_OP(q_l, ldq_l); ALPHA_ST_OP(l_c, stl_c); ALPHA_ST_OP(q_c, stq_c); -#define ALPHA_LDF_OP(name, op) \ -void OPPROTO glue(glue(op_ld, name), MEMSUFFIX) (void) \ -{ \ - print_mem_EA(T0); \ - FT1 = glue(op, MEMSUFFIX)(T0); \ - RETURN(); \ -} - -#define ALPHA_STF_OP(name, op) \ -void OPPROTO glue(glue(op_st, name), MEMSUFFIX) (void) \ -{ \ - print_mem_EA(T0); \ - glue(op, MEMSUFFIX)(T0, FT1); \ - RETURN(); \ -} - -ALPHA_LDF_OP(t, ldfq); -ALPHA_STF_OP(t, stfq); -ALPHA_LDF_OP(s, ldfl); -ALPHA_STF_OP(s, stfl); - -/* VAX floating point */ -ALPHA_LDF_OP(f, helper_ldff); -ALPHA_STF_OP(f, helper_stff); -ALPHA_LDF_OP(g, helper_ldfg); -ALPHA_STF_OP(g, helper_stfg); - #undef MEMSUFFIX diff --git a/target-alpha/op_template.h b/target-alpha/op_template.h deleted file mode 100644 index f2f4b1cf67..0000000000 --- a/target-alpha/op_template.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Alpha emulation cpu micro-operations templates for qemu. - * - * Copyright (c) 2007 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* Optimized constant loads */ -#if REG < 3 - -#if !defined(HOST_SPARC) && !defined(HOST_SPARC64) -void OPPROTO glue(op_reset_FT, REG) (void) -{ - glue(FT, REG) = 0; - RETURN(); -} -#else -void OPPROTO glue(op_reset_FT, REG) (void) -{ - glue(helper_reset_FT, REG)(); - RETURN(); -} -#endif - -#endif /* REG < 3 */ - -#if REG < 31 -/* floating point registers moves */ -void OPPROTO glue(op_load_FT0_fir, REG) (void) -{ - FT0 = env->fir[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_FT1_fir, REG) (void) -{ - FT1 = env->fir[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_FT2_fir, REG) (void) -{ - FT2 = env->fir[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_FT0_fir, REG) (void) -{ - env->fir[REG] = FT0; - RETURN(); -} - -void OPPROTO glue(op_store_FT1_fir, REG) (void) -{ - env->fir[REG] = FT1; - RETURN(); -} - -void OPPROTO glue(op_store_FT2_fir, REG) (void) -{ - env->fir[REG] = FT2; - RETURN(); -} - -void OPPROTO glue(op_cmov_fir, REG) (void) -{ - helper_cmov_fir(REG); - RETURN(); -} -#endif /* REG < 31 */ - -#undef REG diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 9f6084f67c..356ab4d76d 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -48,13 +48,14 @@ struct DisasContext { /* global register indexes */ static TCGv cpu_env; static TCGv cpu_ir[31]; +static TCGv cpu_fir[31]; static TCGv cpu_pc; /* dyngen register indexes */ static TCGv cpu_T[2]; /* register names */ -static char cpu_reg_names[10*4+21*5]; +static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; #include "gen-icount.h" @@ -85,6 +86,11 @@ static void alpha_translate_init(void) cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, ir[i]), p); p += (i < 10) ? 4 : 5; + + sprintf(p, "fir%d", i); + cpu_fir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, fir[i]), p); + p += (i < 10) ? 5 : 6; } cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, @@ -105,69 +111,6 @@ static always_inline void gen_op_nop (void) #endif } -#define GEN32(func, NAME) \ -static GenOpFunc *NAME ## _table [32] = { \ -NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ -NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ -NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ -NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ -NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ -NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ -NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ -NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ -}; \ -static always_inline void func (int n) \ -{ \ - NAME ## _table[n](); \ -} - -/* FIR moves */ -/* Special hacks for fir31 */ -#define gen_op_load_FT0_fir31 gen_op_reset_FT0 -#define gen_op_load_FT1_fir31 gen_op_reset_FT1 -#define gen_op_load_FT2_fir31 gen_op_reset_FT2 -#define gen_op_store_FT0_fir31 gen_op_nop -#define gen_op_store_FT1_fir31 gen_op_nop -#define gen_op_store_FT2_fir31 gen_op_nop -#define gen_op_cmov_fir31 gen_op_nop -GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir); -GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir); -GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir); -GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir); -GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir); -GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir); -GEN32(gen_op_cmov_fir, gen_op_cmov_fir); - -static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn) -{ - switch (Tn) { - case 0: - gen_op_load_FT0_fir(firn); - break; - case 1: - gen_op_load_FT1_fir(firn); - break; - case 2: - gen_op_load_FT2_fir(firn); - break; - } -} - -static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn) -{ - switch (Tn) { - case 0: - gen_op_store_FT0_fir(firn); - break; - case 1: - gen_op_store_FT1_fir(firn); - break; - case 2: - gen_op_store_FT2_fir(firn); - break; - } -} - /* Memory moves */ #if defined(CONFIG_USER_ONLY) #define OP_LD_TABLE(width) \ @@ -218,26 +161,6 @@ GEN_ST(l_c); GEN_LD(q_l); GEN_ST(q_c); -#if 0 /* currently unused */ -GEN_LD(f); -GEN_ST(f); -GEN_LD(g); -GEN_ST(g); -#endif /* 0 */ -GEN_LD(s); -GEN_ST(s); -GEN_LD(t); -GEN_ST(t); - -static always_inline void _gen_op_bcond (DisasContext *ctx) -{ -#if 0 // Qemu does not know how to do this... - gen_op_bcond(ctx->pc); -#else - gen_op_bcond(ctx->pc >> 32, ctx->pc); -#endif -} - static always_inline void gen_excp (DisasContext *ctx, int exception, int error_code) { @@ -277,10 +200,34 @@ static always_inline void gen_load_mem_dyngen (DisasContext *ctx, } } +static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) +{ + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_qemu_ld32u(tmp, t1, flags); + tcg_gen_helper_1_1(helper_memory_to_f, t0, tmp); + tcg_temp_free(tmp); +} + +static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) +{ + TCGv tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_qemu_ld64(tmp, t1, flags); + tcg_gen_helper_1_1(helper_memory_to_g, t0, tmp); + tcg_temp_free(tmp); +} + +static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) +{ + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_qemu_ld32u(tmp, t1, flags); + tcg_gen_helper_1_1(helper_memory_to_s, t0, tmp); + tcg_temp_free(tmp); +} + static always_inline void gen_load_mem (DisasContext *ctx, void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), int ra, int rb, int32_t disp16, - int clear) + int fp, int clear) { TCGv addr; @@ -297,7 +244,10 @@ static always_inline void gen_load_mem (DisasContext *ctx, disp16 &= ~0x7; tcg_gen_movi_i64(addr, disp16); } - tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx); + if (fp) + tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx); + else + tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx); tcg_temp_free(addr); } @@ -319,10 +269,34 @@ static always_inline void gen_store_mem_dyngen (DisasContext *ctx, (*gen_store_op)(ctx); } +static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) +{ + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_helper_1_1(helper_f_to_memory, tmp, t0); + tcg_gen_qemu_st32(tmp, t1, flags); + tcg_temp_free(tmp); +} + +static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) +{ + TCGv tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_helper_1_1(helper_g_to_memory, tmp, t0); + tcg_gen_qemu_st64(tmp, t1, flags); + tcg_temp_free(tmp); +} + +static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) +{ + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_helper_1_1(helper_s_to_memory, tmp, t0); + tcg_gen_qemu_st32(tmp, t1, flags); + tcg_temp_free(tmp); +} + static always_inline void gen_store_mem (DisasContext *ctx, void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), int ra, int rb, int32_t disp16, - int clear) + int fp, int clear) { TCGv addr = tcg_temp_new(TCG_TYPE_I64); if (rb != 31) { @@ -334,9 +308,12 @@ static always_inline void gen_store_mem (DisasContext *ctx, disp16 &= ~0x7; tcg_gen_movi_i64(addr, disp16); } - if (ra != 31) - tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); - else { + if (ra != 31) { + if (fp) + tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx); + else + tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); + } else { TCGv zero = tcg_const_i64(0); tcg_gen_qemu_store(zero, addr, ctx->mem_idx); tcg_temp_free(zero); @@ -344,30 +321,6 @@ static always_inline void gen_store_mem (DisasContext *ctx, tcg_temp_free(addr); } -static always_inline void gen_load_fmem (DisasContext *ctx, - void (*gen_load_fop)(DisasContext *ctx), - int ra, int rb, int32_t disp16) -{ - if (rb != 31) - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16); - else - tcg_gen_movi_i64(cpu_T[0], disp16); - (*gen_load_fop)(ctx); - gen_store_fir(ctx, ra, 1); -} - -static always_inline void gen_store_fmem (DisasContext *ctx, - void (*gen_store_fop)(DisasContext *ctx), - int ra, int rb, int32_t disp16) -{ - if (rb != 31) - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16); - else - tcg_gen_movi_i64(cpu_T[0], disp16); - gen_load_fir(ctx, ra, 1); - (*gen_store_fop)(ctx); -} - static always_inline void gen_bcond (DisasContext *ctx, TCGCond cond, int ra, int32_t disp16, int mask) @@ -398,13 +351,27 @@ static always_inline void gen_bcond (DisasContext *ctx, } static always_inline void gen_fbcond (DisasContext *ctx, - void (*gen_test_op)(void), + void* func, int ra, int32_t disp16) { - tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2)); - gen_load_fir(ctx, ra, 0); - (*gen_test_op)(); - _gen_op_bcond(ctx); + int l1, l2; + TCGv tmp; + + l1 = gen_new_label(); + l2 = gen_new_label(); + if (ra != 31) { + tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]); + } else { + tmp = tcg_const_i64(0); + tcg_gen_helper_1_1(func, tmp, tmp); + } + tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1); + tcg_gen_movi_i64(cpu_pc, ctx->pc); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2)); + gen_set_label(l2); } static always_inline void gen_cmov (DisasContext *ctx, @@ -441,55 +408,69 @@ static always_inline void gen_cmov (DisasContext *ctx, gen_set_label(l1); } -static always_inline void gen_farith2 (DisasContext *ctx, - void (*gen_arith_fop)(void), +static always_inline void gen_farith2 (void *helper, int rb, int rc) { - gen_load_fir(ctx, rb, 0); - (*gen_arith_fop)(); - gen_store_fir(ctx, rc, 0); + if (unlikely(rc == 31)) + return; + + if (rb != 31) + tcg_gen_helper_1_1(helper, cpu_fir[rc], cpu_fir[rb]); + else { + TCGv tmp = tcg_const_i64(0); + tcg_gen_helper_1_1(helper, cpu_fir[rc], tmp); + tcg_temp_free(tmp); + } } -static always_inline void gen_farith3 (DisasContext *ctx, - void (*gen_arith_fop)(void), +static always_inline void gen_farith3 (void *helper, int ra, int rb, int rc) { - gen_load_fir(ctx, ra, 0); - gen_load_fir(ctx, rb, 1); - (*gen_arith_fop)(); - gen_store_fir(ctx, rc, 0); + if (unlikely(rc == 31)) + return; + + if (ra != 31) { + if (rb != 31) + tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); + else { + TCGv tmp = tcg_const_i64(0); + tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp); + tcg_temp_free(tmp); + } + } else { + TCGv tmp = tcg_const_i64(0); + if (rb != 31) + tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]); + else + tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp); + tcg_temp_free(tmp); + } } -static always_inline void gen_fcmov (DisasContext *ctx, - void (*gen_test_fop)(void), +static always_inline void gen_fcmov (void *func, int ra, int rb, int rc) { - gen_load_fir(ctx, ra, 0); - gen_load_fir(ctx, rb, 1); - (*gen_test_fop)(); - gen_op_cmov_fir(rc); -} + int l1; + TCGv tmp; -static always_inline void gen_fti (DisasContext *ctx, - void (*gen_move_fop)(void), - int ra, int rc) -{ - gen_load_fir(ctx, rc, 0); - (*gen_move_fop)(); - if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); -} + if (unlikely(rc == 31)) + return; -static always_inline void gen_itf (DisasContext *ctx, - void (*gen_move_fop)(void), - int ra, int rc) -{ - if (ra != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); + l1 = gen_new_label(); + tmp = tcg_temp_new(TCG_TYPE_I64); + if (ra != 31) { + tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]); + } else { + tmp = tcg_const_i64(0); + tcg_gen_helper_1_1(func, tmp, tmp); + } + tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); + if (rb != 31) + tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); else - tcg_gen_movi_i64(cpu_T[0], 0); - (*gen_move_fop)(); - gen_store_fir(ctx, rc, 0); + tcg_gen_movi_i64(cpu_fir[rc], 0); + gen_set_label(l1); } /* EXTWH, EXTWH, EXTLH, EXTQH */ @@ -704,29 +685,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) /* LDBU */ if (!(ctx->amask & AMASK_BWX)) goto invalid_opc; - gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0); + gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); break; case 0x0B: /* LDQ_U */ - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1); + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); break; case 0x0C: /* LDWU */ if (!(ctx->amask & AMASK_BWX)) goto invalid_opc; - gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 1); + gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 1); break; case 0x0D: /* STW */ - gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); break; case 0x0E: /* STB */ - gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); break; case 0x0F: /* STQ_U */ - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1); + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1); break; case 0x10: switch (fn7) { @@ -1349,47 +1330,64 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) /* ITOFS */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_itf(ctx, &gen_op_itofs, ra, rc); + if (likely(rc != 31)) { + if (ra != 31) { + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); + tcg_gen_helper_1_1(helper_memory_to_s, cpu_fir[rc], tmp); + tcg_temp_free(tmp); + } else + tcg_gen_movi_i64(cpu_fir[rc], 0); + } break; case 0x0A: /* SQRTF */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrtf, rb, rc); + gen_farith2(&helper_sqrtf, rb, rc); break; case 0x0B: /* SQRTS */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrts, rb, rc); + gen_farith2(&helper_sqrts, rb, rc); break; case 0x14: /* ITOFF */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; -#if 0 // TODO - gen_itf(ctx, &gen_op_itoff, ra, rc); -#else - goto invalid_opc; -#endif + if (likely(rc != 31)) { + if (ra != 31) { + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); + tcg_gen_helper_1_1(helper_memory_to_f, cpu_fir[rc], tmp); + tcg_temp_free(tmp); + } else + tcg_gen_movi_i64(cpu_fir[rc], 0); + } break; case 0x24: /* ITOFT */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_itf(ctx, &gen_op_itoft, ra, rc); + if (likely(rc != 31)) { + if (ra != 31) + tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); + else + tcg_gen_movi_i64(cpu_fir[rc], 0); + } break; case 0x2A: /* SQRTG */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrtg, rb, rc); + gen_farith2(&helper_sqrtg, rb, rc); break; case 0x02B: /* SQRTT */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrtt, rb, rc); + gen_farith2(&helper_sqrtt, rb, rc); break; default: goto invalid_opc; @@ -1401,79 +1399,79 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) switch (fpfn) { /* f11 & 0x3F */ case 0x00: /* ADDF */ - gen_farith3(ctx, &gen_op_addf, ra, rb, rc); + gen_farith3(&helper_addf, ra, rb, rc); break; case 0x01: /* SUBF */ - gen_farith3(ctx, &gen_op_subf, ra, rb, rc); + gen_farith3(&helper_subf, ra, rb, rc); break; case 0x02: /* MULF */ - gen_farith3(ctx, &gen_op_mulf, ra, rb, rc); + gen_farith3(&helper_mulf, ra, rb, rc); break; case 0x03: /* DIVF */ - gen_farith3(ctx, &gen_op_divf, ra, rb, rc); + gen_farith3(&helper_divf, ra, rb, rc); break; case 0x1E: /* CVTDG */ #if 0 // TODO - gen_farith2(ctx, &gen_op_cvtdg, rb, rc); + gen_farith2(&helper_cvtdg, rb, rc); #else goto invalid_opc; #endif break; case 0x20: /* ADDG */ - gen_farith3(ctx, &gen_op_addg, ra, rb, rc); + gen_farith3(&helper_addg, ra, rb, rc); break; case 0x21: /* SUBG */ - gen_farith3(ctx, &gen_op_subg, ra, rb, rc); + gen_farith3(&helper_subg, ra, rb, rc); break; case 0x22: /* MULG */ - gen_farith3(ctx, &gen_op_mulg, ra, rb, rc); + gen_farith3(&helper_mulg, ra, rb, rc); break; case 0x23: /* DIVG */ - gen_farith3(ctx, &gen_op_divg, ra, rb, rc); + gen_farith3(&helper_divg, ra, rb, rc); break; case 0x25: /* CMPGEQ */ - gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc); + gen_farith3(&helper_cmpgeq, ra, rb, rc); break; case 0x26: /* CMPGLT */ - gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc); + gen_farith3(&helper_cmpglt, ra, rb, rc); break; case 0x27: /* CMPGLE */ - gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc); + gen_farith3(&helper_cmpgle, ra, rb, rc); break; case 0x2C: /* CVTGF */ - gen_farith2(ctx, &gen_op_cvtgf, rb, rc); + gen_farith2(&helper_cvtgf, rb, rc); break; case 0x2D: /* CVTGD */ #if 0 // TODO - gen_farith2(ctx, &gen_op_cvtgd, rb, rc); + gen_farith2(ctx, &helper_cvtgd, rb, rc); #else goto invalid_opc; #endif break; case 0x2F: /* CVTGQ */ - gen_farith2(ctx, &gen_op_cvtgq, rb, rc); + gen_farith2(&helper_cvtgq, rb, rc); break; case 0x3C: /* CVTQF */ - gen_farith2(ctx, &gen_op_cvtqf, rb, rc); + gen_farith2(&helper_cvtqf, rb, rc); break; case 0x3E: /* CVTQG */ - gen_farith2(ctx, &gen_op_cvtqg, rb, rc); + gen_farith2(&helper_cvtqg, rb, rc); break; default: goto invalid_opc; @@ -1485,73 +1483,73 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) switch (fpfn) { /* f11 & 0x3F */ case 0x00: /* ADDS */ - gen_farith3(ctx, &gen_op_adds, ra, rb, rc); + gen_farith3(&helper_adds, ra, rb, rc); break; case 0x01: /* SUBS */ - gen_farith3(ctx, &gen_op_subs, ra, rb, rc); + gen_farith3(&helper_subs, ra, rb, rc); break; case 0x02: /* MULS */ - gen_farith3(ctx, &gen_op_muls, ra, rb, rc); + gen_farith3(&helper_muls, ra, rb, rc); break; case 0x03: /* DIVS */ - gen_farith3(ctx, &gen_op_divs, ra, rb, rc); + gen_farith3(&helper_divs, ra, rb, rc); break; case 0x20: /* ADDT */ - gen_farith3(ctx, &gen_op_addt, ra, rb, rc); + gen_farith3(&helper_addt, ra, rb, rc); break; case 0x21: /* SUBT */ - gen_farith3(ctx, &gen_op_subt, ra, rb, rc); + gen_farith3(&helper_subt, ra, rb, rc); break; case 0x22: /* MULT */ - gen_farith3(ctx, &gen_op_mult, ra, rb, rc); + gen_farith3(&helper_mult, ra, rb, rc); break; case 0x23: /* DIVT */ - gen_farith3(ctx, &gen_op_divt, ra, rb, rc); + gen_farith3(&helper_divt, ra, rb, rc); break; case 0x24: /* CMPTUN */ - gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc); + gen_farith3(&helper_cmptun, ra, rb, rc); break; case 0x25: /* CMPTEQ */ - gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc); + gen_farith3(&helper_cmpteq, ra, rb, rc); break; case 0x26: /* CMPTLT */ - gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc); + gen_farith3(&helper_cmptlt, ra, rb, rc); break; case 0x27: /* CMPTLE */ - gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc); + gen_farith3(&helper_cmptle, ra, rb, rc); break; case 0x2C: /* XXX: incorrect */ if (fn11 == 0x2AC) { /* CVTST */ - gen_farith2(ctx, &gen_op_cvtst, rb, rc); + gen_farith2(&helper_cvtst, rb, rc); } else { /* CVTTS */ - gen_farith2(ctx, &gen_op_cvtts, rb, rc); + gen_farith2(&helper_cvtts, rb, rc); } break; case 0x2F: /* CVTTQ */ - gen_farith2(ctx, &gen_op_cvttq, rb, rc); + gen_farith2(&helper_cvttq, rb, rc); break; case 0x3C: /* CVTQS */ - gen_farith2(ctx, &gen_op_cvtqs, rb, rc); + gen_farith2(&helper_cvtqs, rb, rc); break; case 0x3E: /* CVTQT */ - gen_farith2(ctx, &gen_op_cvtqt, rb, rc); + gen_farith2(&helper_cvtqt, rb, rc); break; default: goto invalid_opc; @@ -1561,76 +1559,76 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) switch (fn11) { case 0x010: /* CVTLQ */ - gen_farith2(ctx, &gen_op_cvtlq, rb, rc); + gen_farith2(&helper_cvtlq, rb, rc); break; case 0x020: - /* CPYS */ - if (ra == rb) { - if (ra == 31 && rc == 31) { - /* FNOP */ - gen_op_nop(); - } else { + if (likely(rc != 31)) { + if (ra == rb) /* FMOV */ - gen_load_fir(ctx, rb, 0); - gen_store_fir(ctx, rc, 0); - } - } else { - gen_farith3(ctx, &gen_op_cpys, ra, rb, rc); + tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); + else + /* CPYS */ + gen_farith3(&helper_cpys, ra, rb, rc); } break; case 0x021: /* CPYSN */ - gen_farith2(ctx, &gen_op_cpysn, rb, rc); + gen_farith3(&helper_cpysn, ra, rb, rc); break; case 0x022: /* CPYSE */ - gen_farith2(ctx, &gen_op_cpyse, rb, rc); + gen_farith3(&helper_cpyse, ra, rb, rc); break; case 0x024: /* MT_FPCR */ - gen_load_fir(ctx, ra, 0); - gen_op_store_fpcr(); + if (likely(ra != 31)) + tcg_gen_helper_0_1(helper_store_fpcr, cpu_fir[ra]); + else { + TCGv tmp = tcg_const_i64(0); + tcg_gen_helper_0_1(helper_store_fpcr, tmp); + tcg_temp_free(tmp); + } break; case 0x025: /* MF_FPCR */ - gen_op_load_fpcr(); - gen_store_fir(ctx, ra, 0); + if (likely(ra != 31)) + tcg_gen_helper_1_0(helper_load_fpcr, cpu_fir[ra]); break; case 0x02A: /* FCMOVEQ */ - gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc); + gen_fcmov(&helper_cmpfeq, ra, rb, rc); break; case 0x02B: /* FCMOVNE */ - gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc); + gen_fcmov(&helper_cmpfne, ra, rb, rc); break; case 0x02C: /* FCMOVLT */ - gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc); + gen_fcmov(&helper_cmpflt, ra, rb, rc); break; case 0x02D: /* FCMOVGE */ - gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc); + gen_fcmov(&helper_cmpfge, ra, rb, rc); break; case 0x02E: /* FCMOVLE */ - gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc); + gen_fcmov(&helper_cmpfle, ra, rb, rc); break; case 0x02F: /* FCMOVGT */ - gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc); + gen_fcmov(&helper_cmpfgt, ra, rb, rc); break; case 0x030: /* CVTQL */ - gen_farith2(ctx, &gen_op_cvtql, rb, rc); + gen_farith2(&helper_cvtql, rb, rc); break; case 0x130: /* CVTQL/V */ - gen_farith2(ctx, &gen_op_cvtqlv, rb, rc); + gen_farith2(&helper_cvtqlv, rb, rc); break; case 0x530: /* CVTQL/SV */ - gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc); + gen_farith2(&helper_cvtqlsv, rb, rc); break; default: goto invalid_opc; @@ -1981,13 +1979,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) /* FTOIT */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_fti(ctx, &gen_op_ftoit, ra, rb); + if (likely(rc != 31)) { + if (ra != 31) + tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); + else + tcg_gen_movi_i64(cpu_ir[rc], 0); + } break; case 0x78: /* FTOIS */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_fti(ctx, &gen_op_ftois, ra, rb); + if (rc != 31) { + TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32); + if (ra != 31) + tcg_gen_helper_1_1(helper_s_to_memory, tmp1, cpu_fir[ra]); + else { + TCGv tmp2 = tcg_const_i64(0); + tcg_gen_helper_1_1(helper_s_to_memory, tmp1, tmp2); + tcg_temp_free(tmp2); + } + tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); + tcg_temp_free(tmp1); + } break; default: goto invalid_opc; @@ -2116,59 +2130,43 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) #endif case 0x20: /* LDF */ -#if 0 // TODO - gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); break; case 0x21: /* LDG */ -#if 0 // TODO - gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); break; case 0x22: /* LDS */ - gen_load_fmem(ctx, &gen_lds, ra, rb, disp16); + gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); break; case 0x23: /* LDT */ - gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16); + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); break; case 0x24: /* STF */ -#if 0 // TODO - gen_store_fmem(ctx, &gen_stf, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); break; case 0x25: /* STG */ -#if 0 // TODO - gen_store_fmem(ctx, &gen_stg, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); break; case 0x26: /* STS */ - gen_store_fmem(ctx, &gen_sts, ra, rb, disp16); + gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); break; case 0x27: /* STT */ - gen_store_fmem(ctx, &gen_stt, ra, rb, disp16); + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); break; case 0x28: /* LDL */ - gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0); + gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); break; case 0x29: /* LDQ */ - gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0); + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); break; case 0x2A: /* LDL_L */ @@ -2180,11 +2178,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x2C: /* STL */ - gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0); break; case 0x2D: /* STQ */ - gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0); break; case 0x2E: /* STL_C */ @@ -2203,17 +2201,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x31: /* FBEQ */ - gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16); + gen_fbcond(ctx, &helper_cmpfeq, ra, disp16); ret = 1; break; case 0x32: /* FBLT */ - gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16); + gen_fbcond(ctx, &helper_cmpflt, ra, disp16); ret = 1; break; case 0x33: /* FBLE */ - gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16); + gen_fbcond(ctx, &helper_cmpfle, ra, disp16); ret = 1; break; case 0x34: @@ -2225,17 +2223,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x35: /* FBNE */ - gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16); + gen_fbcond(ctx, &helper_cmpfne, ra, disp16); ret = 1; break; case 0x36: /* FBGE */ - gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16); + gen_fbcond(ctx, &helper_cmpfge, ra, disp16); ret = 1; break; case 0x37: /* FBGT */ - gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16); + gen_fbcond(ctx, &helper_cmpfgt, ra, disp16); ret = 1; break; case 0x38: -- cgit v1.2.1