From 8af35c37d296daa463c0d4ed575a51729afc7f6d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 26 Feb 2014 17:20:02 +0000 Subject: target-arm: Implement AArch64 cache invalidate/clean ops Implement all the AArch64 cache invalidate and clean ops (which are all NOPs since QEMU doesn't emulate the cache). The only remaining unimplemented cache op is DC ZVA. Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target-arm/cpu.c') diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8fed098842..2f949437fd 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -91,8 +91,8 @@ static void arm_cpu_reset(CPUState *s) env->aarch64 = 1; #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; - /* Userspace expects access to CTL_EL0 */ - env->cp15.c1_sys |= SCTLR_UCT; + /* Userspace expects access to CTL_EL0 and the cache ops */ + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; #else env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F | PSTATE_MODE_EL1h; -- cgit v1.2.1