From 7c2cb42b5033a851aa2a81de8d8a9e75bb65c2b6 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 10 Mar 2014 14:56:28 +0000 Subject: target-arm: Implements the ARM PMCCNTR register This patch implements the ARM PMCCNTR register including the disable and reset components of the PMCR register. Signed-off-by: Alistair Francis Message-id: bbf405e1feaf352cf39d5db402c9efcbd0f57c78.1393459802.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell --- target-arm/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'target-arm/cpu.h') diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 49fef3fcbe..0a7edfe6cb 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -222,6 +222,10 @@ typedef struct CPUARMState { uint64_t dbgbcr[16]; /* breakpoint control registers */ uint64_t dbgwvr[16]; /* watchpoint value registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */ + /* If the counter is enabled, this stores the last time the counter + * was reset. Otherwise it stores the counter value + */ + uint32_t c15_ccnt; } cp15; struct { -- cgit v1.2.1