From 48eb3ae64b3e17151cf8f42af185e6f43baf707b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 19 Aug 2014 18:56:25 +0100 Subject: target-arm: Adjust debug ID registers per-CPU Allow each CPU type to specify the value for the debug ID registers, by putting them in the ARMCPU struct, and use the resulting information to only expose the correct number of watchpoint and breakpoint registers for the CPU. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target-arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target-arm/cpu64.c') diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 8b2081c246..38d2b8445a 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -127,6 +127,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_aa64dfr0 = 0x10305106; cpu->id_aa64isar0 = 0x00010000; cpu->id_aa64mmfr0 = 0x00001124; + cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ -- cgit v1.2.1