From 1edee4708a0e3163cbf20fac325be456abd960bb Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Mon, 14 Sep 2015 14:39:50 +0100 Subject: target-arm: Suppress TBI for S2 translations Stage-2 MMU translations do not have configurable TBI as the top byte is always 0 (48-bit IPAs). Signed-off-by: Edgar E. Iglesias Message-id: 1442135278-25281-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target-arm/helper.c') diff --git a/target-arm/helper.c b/target-arm/helper.c index d84f3c94f7..200b9f2e9f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6370,7 +6370,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (arm_el_is_aa64(env, el)) { va_size = 64; if (el > 1) { - tbi = extract64(tcr->raw_tcr, 20, 1); + if (mmu_idx != ARMMMUIdx_S2NS) { + tbi = extract64(tcr->raw_tcr, 20, 1); + } } else { if (extract64(address, 55, 1)) { tbi = extract64(tcr->raw_tcr, 38, 1); -- cgit v1.2.1