From cd4da6317748e3ae2bed5fcc5fb3f81e5c853446 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 26 Feb 2014 17:20:02 +0000 Subject: target-arm: Implement AArch64 MIDR_EL1 Implement the AArch64 view of the MIDR system register (for AArch64 it is a simple constant, unlike the complicated mess that TI925 imposes on the 32-bit view). Signed-off-by: Peter Maydell Reviewed-by: Peter Crosthwaite --- target-arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target-arm/helper.c') diff --git a/target-arm/helper.c b/target-arm/helper.c index ff1ed7d551..e5575338ff 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1720,6 +1720,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .type = ARM_CP_OVERRIDE }, + { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0, + .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST }, { .name = "CTR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, -- cgit v1.2.1