From 1b505f93bcf605e7c4144fef83bd039b0d4f2576 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 1 May 2014 15:24:45 +0100 Subject: target-arm: A64: Handle blr lr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For linked branches, updates to the link register happen conceptually after the read of the branch target register. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Cc: qemu-stable@nongnu.org Message-id: 1398926097-28097-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target-arm/translate-a64.c') diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index e31e069041..b62db4d566 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1509,8 +1509,10 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) switch (opc) { case 0: /* BR */ case 2: /* RET */ + tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); break; case 1: /* BLR */ + tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); break; case 4: /* ERET */ @@ -1529,7 +1531,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) return; } - tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); s->is_jmp = DISAS_JUMP; } -- cgit v1.2.1