From fdfba1a298ae26dd44bcfdb0429314139a0bc55a Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Fri, 15 Nov 2013 14:46:38 +0100 Subject: exec: Make ldl_*_phys input an AddressSpace Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias --- target-i386/arch_memory_mapping.c | 36 ++++++------- target-i386/helper.c | 9 ++-- target-i386/seg_helper.c | 6 ++- target-i386/smm_helper.c | 103 ++++++++++++++++++++------------------ target-i386/svm_helper.c | 28 ++++++----- 5 files changed, 97 insertions(+), 85 deletions(-) (limited to 'target-i386') diff --git a/target-i386/arch_memory_mapping.c b/target-i386/arch_memory_mapping.c index 462f984a26..a1947092fc 100644 --- a/target-i386/arch_memory_mapping.c +++ b/target-i386/arch_memory_mapping.c @@ -16,7 +16,8 @@ #include "sysemu/memory_mapping.h" /* PAE Paging or IA-32e Paging */ -static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr, +static void walk_pte(MemoryMappingList *list, AddressSpace *as, + hwaddr pte_start_addr, int32_t a20_mask, target_ulong start_line_addr) { hwaddr pte_addr, start_paddr; @@ -45,7 +46,7 @@ static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr, } /* 32-bit Paging */ -static void walk_pte2(MemoryMappingList *list, +static void walk_pte2(MemoryMappingList *list, AddressSpace *as, hwaddr pte_start_addr, int32_t a20_mask, target_ulong start_line_addr) { @@ -56,7 +57,7 @@ static void walk_pte2(MemoryMappingList *list, for (i = 0; i < 1024; i++) { pte_addr = (pte_start_addr + i * 4) & a20_mask; - pte = ldl_phys(pte_addr); + pte = ldl_phys(as, pte_addr); if (!(pte & PG_PRESENT_MASK)) { /* not present */ continue; @@ -77,7 +78,8 @@ static void walk_pte2(MemoryMappingList *list, /* PAE Paging or IA-32e Paging */ #define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */ -static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr, +static void walk_pde(MemoryMappingList *list, AddressSpace *as, + hwaddr pde_start_addr, int32_t a20_mask, target_ulong start_line_addr) { hwaddr pde_addr, pte_start_addr, start_paddr; @@ -108,12 +110,12 @@ static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr, } pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask; - walk_pte(list, pte_start_addr, a20_mask, line_addr); + walk_pte(list, as, pte_start_addr, a20_mask, line_addr); } } /* 32-bit Paging */ -static void walk_pde2(MemoryMappingList *list, +static void walk_pde2(MemoryMappingList *list, AddressSpace *as, hwaddr pde_start_addr, int32_t a20_mask, bool pse) { @@ -124,7 +126,7 @@ static void walk_pde2(MemoryMappingList *list, for (i = 0; i < 1024; i++) { pde_addr = (pde_start_addr + i * 4) & a20_mask; - pde = ldl_phys(pde_addr); + pde = ldl_phys(as, pde_addr); if (!(pde & PG_PRESENT_MASK)) { /* not present */ continue; @@ -150,12 +152,12 @@ static void walk_pde2(MemoryMappingList *list, } pte_start_addr = (pde & ~0xfff) & a20_mask; - walk_pte2(list, pte_start_addr, a20_mask, line_addr); + walk_pte2(list, as, pte_start_addr, a20_mask, line_addr); } } /* PAE Paging */ -static void walk_pdpe2(MemoryMappingList *list, +static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as, hwaddr pdpe_start_addr, int32_t a20_mask) { hwaddr pdpe_addr, pde_start_addr; @@ -173,13 +175,13 @@ static void walk_pdpe2(MemoryMappingList *list, line_addr = (((unsigned int)i & 0x3) << 30); pde_start_addr = (pdpe & ~0xfff) & a20_mask; - walk_pde(list, pde_start_addr, a20_mask, line_addr); + walk_pde(list, as, pde_start_addr, a20_mask, line_addr); } } #ifdef TARGET_X86_64 /* IA-32e Paging */ -static void walk_pdpe(MemoryMappingList *list, +static void walk_pdpe(MemoryMappingList *list, AddressSpace *as, hwaddr pdpe_start_addr, int32_t a20_mask, target_ulong start_line_addr) { @@ -211,12 +213,12 @@ static void walk_pdpe(MemoryMappingList *list, } pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask; - walk_pde(list, pde_start_addr, a20_mask, line_addr); + walk_pde(list, as, pde_start_addr, a20_mask, line_addr); } } /* IA-32e Paging */ -static void walk_pml4e(MemoryMappingList *list, +static void walk_pml4e(MemoryMappingList *list, AddressSpace *as, hwaddr pml4e_start_addr, int32_t a20_mask) { hwaddr pml4e_addr, pdpe_start_addr; @@ -234,7 +236,7 @@ static void walk_pml4e(MemoryMappingList *list, line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48); pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask; - walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr); + walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr); } } #endif @@ -256,14 +258,14 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, hwaddr pml4e_addr; pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask; - walk_pml4e(list, pml4e_addr, env->a20_mask); + walk_pml4e(list, cs->as, pml4e_addr, env->a20_mask); } else #endif { hwaddr pdpe_addr; pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask; - walk_pdpe2(list, pdpe_addr, env->a20_mask); + walk_pdpe2(list, cs->as, pdpe_addr, env->a20_mask); } } else { hwaddr pde_addr; @@ -271,7 +273,7 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list, pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask; pse = !!(env->cr[4] & CR4_PSE_MASK); - walk_pde2(list, pde_addr, env->a20_mask, pse); + walk_pde2(list, cs->as, pde_addr, env->a20_mask, pse); } } diff --git a/target-i386/helper.c b/target-i386/helper.c index fe613b26e1..2899779502 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -515,6 +515,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, int is_write1, int mmu_idx) { + CPUState *cs = ENV_GET_CPU(env); uint64_t ptep, pte; target_ulong pde_addr, pte_addr; int error_code, is_dirty, prot, page_size, is_write, is_user; @@ -734,7 +735,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, /* page directory entry */ pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask; - pde = ldl_phys(pde_addr); + pde = ldl_phys(cs->as, pde_addr); if (!(pde & PG_PRESENT_MASK)) { error_code = 0; goto do_fault; @@ -792,7 +793,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, /* page directory entry */ pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask; - pte = ldl_phys(pte_addr); + pte = ldl_phys(cs->as, pte_addr); if (!(pte & PG_PRESENT_MASK)) { error_code = 0; goto do_fault; @@ -963,7 +964,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) /* page directory entry */ pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask; - pde = ldl_phys(pde_addr); + pde = ldl_phys(cs->as, pde_addr); if (!(pde & PG_PRESENT_MASK)) return -1; if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { @@ -972,7 +973,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } else { /* page directory entry */ pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask; - pte = ldl_phys(pte_addr); + pte = ldl_phys(cs->as, pte_addr); if (!(pte & PG_PRESENT_MASK)) return -1; page_size = 4096; diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index e78910200a..6b18b3e41e 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -1131,7 +1131,8 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int, static void handle_even_inj(CPUX86State *env, int intno, int is_int, int error_code, int is_hw, int rm) { - uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, + CPUState *cs = ENV_GET_CPU(env); + uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); if (!(event_inj & SVM_EVTINJ_VALID)) { @@ -1225,7 +1226,8 @@ static void do_interrupt_all(X86CPU *cpu, int intno, int is_int, #if !defined(CONFIG_USER_ONLY) if (env->hflags & HF_SVMI_MASK) { - uint32_t event_inj = ldl_phys(env->vm_vmcb + + CPUState *cs = CPU(cpu); + uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 6cb45511b8..67a73c06d1 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -180,6 +180,7 @@ void do_smm_enter(X86CPU *cpu) void helper_rsm(CPUX86State *env) { + CPUState *cs = ENV_GET_CPU(env); X86CPU *cpu = x86_env_get_cpu(env); target_ulong sm_state; int i, offset; @@ -194,25 +195,25 @@ void helper_rsm(CPUX86State *env) cpu_x86_load_seg_cache(env, i, lduw_phys(sm_state + offset), ldq_phys(sm_state + offset + 8), - ldl_phys(sm_state + offset + 4), + ldl_phys(cs->as, sm_state + offset + 4), (lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8); } env->gdt.base = ldq_phys(sm_state + 0x7e68); - env->gdt.limit = ldl_phys(sm_state + 0x7e64); + env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64); env->ldt.selector = lduw_phys(sm_state + 0x7e70); env->ldt.base = ldq_phys(sm_state + 0x7e78); - env->ldt.limit = ldl_phys(sm_state + 0x7e74); + env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7e74); env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8; env->idt.base = ldq_phys(sm_state + 0x7e88); - env->idt.limit = ldl_phys(sm_state + 0x7e84); + env->idt.limit = ldl_phys(cs->as, sm_state + 0x7e84); env->tr.selector = lduw_phys(sm_state + 0x7e90); env->tr.base = ldq_phys(sm_state + 0x7e98); - env->tr.limit = ldl_phys(sm_state + 0x7e94); + env->tr.limit = ldl_phys(cs->as, sm_state + 0x7e94); env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8; env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8); @@ -227,51 +228,51 @@ void helper_rsm(CPUX86State *env) env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8); } env->eip = ldq_phys(sm_state + 0x7f78); - cpu_load_eflags(env, ldl_phys(sm_state + 0x7f70), + cpu_load_eflags(env, ldl_phys(cs->as, sm_state + 0x7f70), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); - env->dr[6] = ldl_phys(sm_state + 0x7f68); - env->dr[7] = ldl_phys(sm_state + 0x7f60); + env->dr[6] = ldl_phys(cs->as, sm_state + 0x7f68); + env->dr[7] = ldl_phys(cs->as, sm_state + 0x7f60); - cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48)); - cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50)); - cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58)); + cpu_x86_update_cr4(env, ldl_phys(cs->as, sm_state + 0x7f48)); + cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7f50)); + cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7f58)); - val = ldl_phys(sm_state + 0x7efc); /* revision ID */ + val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { - env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff; + env->smbase = ldl_phys(cs->as, sm_state + 0x7f00) & ~0x7fff; } #else - cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc)); - cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8)); - cpu_load_eflags(env, ldl_phys(sm_state + 0x7ff4), + cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7ffc)); + cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7ff8)); + cpu_load_eflags(env, ldl_phys(cs->as, sm_state + 0x7ff4), ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); - env->eip = ldl_phys(sm_state + 0x7ff0); - env->regs[R_EDI] = ldl_phys(sm_state + 0x7fec); - env->regs[R_ESI] = ldl_phys(sm_state + 0x7fe8); - env->regs[R_EBP] = ldl_phys(sm_state + 0x7fe4); - env->regs[R_ESP] = ldl_phys(sm_state + 0x7fe0); - env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc); - env->regs[R_EDX] = ldl_phys(sm_state + 0x7fd8); - env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4); - env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0); - env->dr[6] = ldl_phys(sm_state + 0x7fcc); - env->dr[7] = ldl_phys(sm_state + 0x7fc8); - - env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff; - env->tr.base = ldl_phys(sm_state + 0x7f64); - env->tr.limit = ldl_phys(sm_state + 0x7f60); - env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8; - - env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff; - env->ldt.base = ldl_phys(sm_state + 0x7f80); - env->ldt.limit = ldl_phys(sm_state + 0x7f7c); - env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8; - - env->gdt.base = ldl_phys(sm_state + 0x7f74); - env->gdt.limit = ldl_phys(sm_state + 0x7f70); - - env->idt.base = ldl_phys(sm_state + 0x7f58); - env->idt.limit = ldl_phys(sm_state + 0x7f54); + env->eip = ldl_phys(cs->as, sm_state + 0x7ff0); + env->regs[R_EDI] = ldl_phys(cs->as, sm_state + 0x7fec); + env->regs[R_ESI] = ldl_phys(cs->as, sm_state + 0x7fe8); + env->regs[R_EBP] = ldl_phys(cs->as, sm_state + 0x7fe4); + env->regs[R_ESP] = ldl_phys(cs->as, sm_state + 0x7fe0); + env->regs[R_EBX] = ldl_phys(cs->as, sm_state + 0x7fdc); + env->regs[R_EDX] = ldl_phys(cs->as, sm_state + 0x7fd8); + env->regs[R_ECX] = ldl_phys(cs->as, sm_state + 0x7fd4); + env->regs[R_EAX] = ldl_phys(cs->as, sm_state + 0x7fd0); + env->dr[6] = ldl_phys(cs->as, sm_state + 0x7fcc); + env->dr[7] = ldl_phys(cs->as, sm_state + 0x7fc8); + + env->tr.selector = ldl_phys(cs->as, sm_state + 0x7fc4) & 0xffff; + env->tr.base = ldl_phys(cs->as, sm_state + 0x7f64); + env->tr.limit = ldl_phys(cs->as, sm_state + 0x7f60); + env->tr.flags = (ldl_phys(cs->as, sm_state + 0x7f5c) & 0xf0ff) << 8; + + env->ldt.selector = ldl_phys(cs->as, sm_state + 0x7fc0) & 0xffff; + env->ldt.base = ldl_phys(cs->as, sm_state + 0x7f80); + env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7f7c); + env->ldt.flags = (ldl_phys(cs->as, sm_state + 0x7f78) & 0xf0ff) << 8; + + env->gdt.base = ldl_phys(cs->as, sm_state + 0x7f74); + env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7f70); + + env->idt.base = ldl_phys(cs->as, sm_state + 0x7f58); + env->idt.limit = ldl_phys(cs->as, sm_state + 0x7f54); for (i = 0; i < 6; i++) { if (i < 3) { @@ -280,16 +281,18 @@ void helper_rsm(CPUX86State *env) offset = 0x7f2c + (i - 3) * 12; } cpu_x86_load_seg_cache(env, i, - ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff, - ldl_phys(sm_state + offset + 8), - ldl_phys(sm_state + offset + 4), - (ldl_phys(sm_state + offset) & 0xf0ff) << 8); + ldl_phys(cs->as, + sm_state + 0x7fa8 + i * 4) & 0xffff, + ldl_phys(cs->as, sm_state + offset + 8), + ldl_phys(cs->as, sm_state + offset + 4), + (ldl_phys(cs->as, + sm_state + offset) & 0xf0ff) << 8); } - cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14)); + cpu_x86_update_cr4(env, ldl_phys(cs->as, sm_state + 0x7f14)); - val = ldl_phys(sm_state + 0x7efc); /* revision ID */ + val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { - env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff; + env->smbase = ldl_phys(cs->as, sm_state + 0x7ef8) & ~0x7fff; } #endif CC_OP = CC_OP_EFLAGS; diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index 4a7de42b35..6c3c8bf4e3 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -101,11 +101,12 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr, static inline void svm_load_seg(CPUX86State *env, hwaddr addr, SegmentCache *sc) { + CPUState *cs = ENV_GET_CPU(env); unsigned int flags; sc->selector = lduw_phys(addr + offsetof(struct vmcb_seg, selector)); sc->base = ldq_phys(addr + offsetof(struct vmcb_seg, base)); - sc->limit = ldl_phys(addr + offsetof(struct vmcb_seg, limit)); + sc->limit = ldl_phys(cs->as, addr + offsetof(struct vmcb_seg, limit)); flags = lduw_phys(addr + offsetof(struct vmcb_seg, attrib)); sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12); } @@ -122,6 +123,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr, void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { + CPUState *cs = ENV_GET_CPU(env); target_ulong addr; uint32_t event_inj; uint32_t int_ctl; @@ -190,7 +192,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->intercept_dr_write = lduw_phys(env->vm_vmcb + offsetof(struct vmcb, control.intercept_dr_write)); - env->intercept_exceptions = ldl_phys(env->vm_vmcb + + env->intercept_exceptions = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.intercept_exceptions )); @@ -203,12 +205,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->gdt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base)); - env->gdt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, + env->gdt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit)); env->idt.base = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.idtr.base)); - env->idt.limit = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, + env->idt.limit = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit)); /* clear exit_info_2 so we behave like the real hardware */ @@ -221,7 +223,8 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_x86_update_cr3(env, ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3))); env->cr[2] = ldq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr2)); - int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); + int_ctl = ldl_phys(cs->as, + env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK); if (int_ctl & V_INTR_MASKING_MASK) { env->v_tpr = int_ctl & V_TPR_MASK; @@ -277,12 +280,12 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) } /* maybe we need to inject an event */ - event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, + event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); if (event_inj & SVM_EVTINJ_VALID) { uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK; uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR; - uint32_t event_inj_err = ldl_phys(env->vm_vmcb + + uint32_t event_inj_err = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj_err)); @@ -594,7 +597,8 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]); stq_phys(env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]); - int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); + int_ctl = ldl_phys(cs->as, + env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK); int_ctl |= env->v_tpr & V_TPR_MASK; if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { @@ -623,12 +627,12 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.gdtr.base)); - env->gdt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, + env->gdt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit)); env->idt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.idtr.base)); - env->idt.limit = ldl_phys(env->vm_hsave + offsetof(struct vmcb, + env->idt.limit = ldl_phys(cs->as, env->vm_hsave + offsetof(struct vmcb, save.idtr.limit)); cpu_x86_update_cr0(env, ldq_phys(env->vm_hsave + offsetof(struct vmcb, @@ -674,10 +678,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) exit_info_1); stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info), - ldl_phys(env->vm_vmcb + offsetof(struct vmcb, + ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj))); stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err), - ldl_phys(env->vm_vmcb + offsetof(struct vmcb, + ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb, control.event_inj_err))); stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0); 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