From 118d1e4f59c36078a0d76d090d4c16deace47233 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Mon, 13 May 2013 17:14:35 +0200 Subject: target-mips: set carry bit correctly in DSPControl register First we need to clear the bit and then we set the given value. Instruction ADDSC sets the bit and instruction ADDWC uses this bit. Signed-off-by: Petar Jovanovic Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'target-mips/dsp_helper.c') diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 655dc8a944..918a898699 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -54,9 +54,10 @@ static inline void set_DSPControl_overflow_flag(uint32_t flag, int position, env->active_tc.DSPControl |= (target_ulong)flag << position; } -static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env) +static inline void set_DSPControl_carryflag(bool flag, CPUMIPSState *env) { - env->active_tc.DSPControl |= (target_ulong)flag << 13; + env->active_tc.DSPControl &= ~(1 << 13); + env->active_tc.DSPControl |= flag << 13; } static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env) @@ -1267,7 +1268,7 @@ SUBUH_QB(subuh_r, 1); target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env) { uint64_t temp, tempRs, tempRt; - int32_t flag; + bool flag; tempRs = (uint64_t)rs & MIPSDSP_LLO; tempRt = (uint64_t)rt & MIPSDSP_LLO; -- cgit v1.2.1