From 68473f15d4c9948986618f63828825beafcaf1cf Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 10 Feb 2013 10:30:46 -0800 Subject: mips64-linux-user: Enable 64-bit address mode and fpu Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'target-mips/translate.c') diff --git a/target-mips/translate.c b/target-mips/translate.c index a51f4303ab..694f07c49f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15944,6 +15944,14 @@ void cpu_state_reset(CPUMIPSState *env) #if defined(CONFIG_USER_ONLY) env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); +# ifdef TARGET_MIPS64 + /* Enable 64-bit register mode. */ + env->CP0_Status |= (1 << CP0St_PX); +# endif +# ifdef TARGET_ABI_MIPSN64 + /* Enable 64-bit address mode. */ + env->CP0_Status |= (1 << CP0St_UX); +# endif /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR hardware registers. */ env->CP0_HWREna |= 0x0000000F; @@ -15953,6 +15961,10 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { env->CP0_Status |= (1 << CP0St_MX); } + /* Enable 64-bit FPU if the target cpu supports it. */ + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->CP0_Status |= (1 << CP0St_FR); + } #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, -- cgit v1.2.1