From a6763a588127d8b0f7e64312e9153c6c6bae822f Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Wed, 9 May 2007 09:33:33 +0000
Subject: Fix MIPS64 address computation specialcase, by Aurelien Jarno.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2793 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-mips/op.c        | 16 ++++++++++++++++
 target-mips/translate.c |  4 ++--
 2 files changed, 18 insertions(+), 2 deletions(-)

(limited to 'target-mips')

diff --git a/target-mips/op.c b/target-mips/op.c
index aedd7bd84e..9b0cee0e35 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -289,6 +289,22 @@ void op_store_LO (void)
 #undef MEMSUFFIX
 #endif
 
+/* Addresses computation */
+void op_addr_add (void)
+{
+/* For compatibility with 32-bit code, data reference in user mode
+   with Status_UX = 0 should be casted to 32-bit and sign extended.
+   See the MIPS64 PRA manual, section 4.10. */
+#ifdef TARGET_MIPS64
+    if ((env->CP0_Status & (1 << CP0St_UM)) &&
+        !(env->CP0_Status & (1 << CP0St_UX)))
+        T0 = (int64_t)(int32_t)(T0 + T1);
+    else
+#endif
+        T0 += T1;
+    RETURN();
+}
+
 /* Arithmetic */
 void op_add (void)
 {
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6098b2a10b..debe17d7c6 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -719,7 +719,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
     } else {
         gen_op_load_gpr_T0(base);
         gen_op_set_T1(offset);
-        gen_op_add();
+        gen_op_addr_add();
     }
     /* Don't do NOP if destination is zero: we must perform the actual
      * memory access
@@ -868,7 +868,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
     } else {
         gen_op_load_gpr_T0(base);
         gen_op_set_T1(offset);
-        gen_op_add();
+        gen_op_addr_add();
     }
     /* Don't do NOP if destination is zero: we must perform the actual
      * memory access
-- 
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