From cb269f273fdbdb26ddb1cba4a0fe2249418a8e77 Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Fri, 7 Nov 2014 10:43:21 +0000 Subject: target-mips: fix multiple TCG registers covering same data Avoid to allocate different TCG registers for the FPU registers that are mapped on the MSA vectore registers. Signed-off-by: Yongbok Kim Reviewed-by: Richard Henderson Signed-off-by: Leon Alrae --- target-mips/translate.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'target-mips') diff --git a/target-mips/translate.c b/target-mips/translate.c index 0bea3c44cb..f0b8e6ffe4 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19284,15 +19284,13 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); - for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i]); - fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]); - } - for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]); + /* The scalar floating-point unit (FPU) registers are mapped on + * the MSA vector registers. */ + fpu_f64[i] = msa_wr_d[i * 2]; off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]); -- cgit v1.2.1