From 4b69c7e265a2c2fd1120c431c5d8d0809d4ec10a Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 17 Jun 2014 23:10:26 +0100 Subject: target-mips: Reset CPU timer consistently The MIPS CPU timer (CP0 Count/Compare registers & QEMU timer) is reset at machine initialisation, including starting the timeout. Both registers however are placed before mvp in CPUMIPSState so they will both be zeroed on reset by the memset in mips_cpu_reset() including soon after init. This doesn't take into account that the timer may be running, in which case env->CP0_Count will represent the delta against the VM clock and the timeout will need updating. At init time (cpu_mips_clock_init()), lets only create the timer. Setting Count = 1 and starting the timer (cpu_mips_store_count()) can be done at reset time from cpu_state_reset(), which is after the memset. There is also no need to set CP0_Compare = 0 as that is already handled by the memset. Note that a reset occurs from mips_cpu_realizefn() which is before the machine init callback has had a chance to set up the CPU interrupts and the CPU timer, so env->timer will be NULL. This case is handled explicitly in cpu_mips_store_count(), treating the timer as disabled (which will also be the right thing to do when KVM support is added). Reported-by: Paolo Bonzini Signed-off-by: James Hogan Cc: Aurelien Jarno Signed-off-by: Paolo Bonzini --- target-mips/translate.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target-mips') diff --git a/target-mips/translate.c b/target-mips/translate.c index 76deb7b138..d95ab9efe7 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -16043,6 +16043,8 @@ void cpu_state_reset(CPUMIPSState *env) /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); + cpu_mips_store_count(env, 1); + if (env->CP0_Config3 & (1 << CP0C3_MT)) { int i; -- cgit v1.2.1 From 22010ce7f23236b970b40cc5c0cf0c7fe0588e2f Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 17 Jun 2014 23:10:29 +0100 Subject: target-mips: get_physical_address: Add defines for segment bases Add preprocessor definitions for 32bit segment bases for use in get_physical_address(). These will also be taken advantage of in the next patch which adds KVM awareness. Signed-off-by: James Hogan Reviewed-by: Aurelien Jarno Signed-off-by: Paolo Bonzini --- target-mips/helper.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'target-mips') diff --git a/target-mips/helper.c b/target-mips/helper.c index 064622cc31..caacd762fd 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -118,7 +118,13 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, qemu_log("user mode %d h %08x\n", user_mode, env->hflags); #endif - if (address <= (int32_t)0x7FFFFFFFUL) { +#define USEG_LIMIT 0x7FFFFFFFUL +#define KSEG0_BASE 0x80000000UL +#define KSEG1_BASE 0xA0000000UL +#define KSEG2_BASE 0xC0000000UL +#define KSEG3_BASE 0xE0000000UL + + if (address <= USEG_LIMIT) { /* useg */ if (env->CP0_Status & (1 << CP0St_ERL)) { *physical = address & 0xFFFFFFFF; @@ -160,23 +166,23 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, ret = TLBRET_BADADDR; } #endif - } else if (address < (int32_t)0xA0000000UL) { + } else if (address < (int32_t)KSEG1_BASE) { /* kseg0 */ if (kernel_mode) { - *physical = address - (int32_t)0x80000000UL; + *physical = address - (int32_t)KSEG0_BASE; *prot = PAGE_READ | PAGE_WRITE; } else { ret = TLBRET_BADADDR; } - } else if (address < (int32_t)0xC0000000UL) { + } else if (address < (int32_t)KSEG2_BASE) { /* kseg1 */ if (kernel_mode) { - *physical = address - (int32_t)0xA0000000UL; + *physical = address - (int32_t)KSEG1_BASE; *prot = PAGE_READ | PAGE_WRITE; } else { ret = TLBRET_BADADDR; } - } else if (address < (int32_t)0xE0000000UL) { + } else if (address < (int32_t)KSEG3_BASE) { /* sseg (kseg2) */ if (supervisor_mode || kernel_mode) { ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); -- cgit v1.2.1 From 4ef37e6907eaeeec3e0425b9e51a4b3918c194c7 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 17 Jun 2014 23:10:30 +0100 Subject: target-mips: get_physical_address: Add KVM awareness MIPS KVM trap & emulate mode (which is currently the only supported mode) has to add an extra kseg0/kseg1 at 0x40000000 and an extra kseg2/kseg3 at 0x60000000. Take this into account in get_physical_address() so that debug memory access works. This is done by translating the address to a standard kseg0 or kseg2 address before doing the normal address translation. The real virtual address is still used for TLB lookups. Signed-off-by: James Hogan Cc: Aurelien Jarno Signed-off-by: Paolo Bonzini --- target-mips/helper.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) (limited to 'target-mips') diff --git a/target-mips/helper.c b/target-mips/helper.c index caacd762fd..8a997e44e5 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -24,6 +24,7 @@ #include #include "cpu.h" +#include "sysemu/kvm.h" enum { TLBRET_DIRTY = -4, @@ -100,7 +101,7 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, } static int get_physical_address (CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong address, + int *prot, target_ulong real_address, int rw, int access_type) { /* User mode can only access useg/xuseg */ @@ -113,6 +114,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; #endif int ret = TLBRET_MATCH; + /* effective address (modified for KVM T&E kernel segments) */ + target_ulong address = real_address; #if 0 qemu_log("user mode %d h %08x\n", user_mode, env->hflags); @@ -124,19 +127,35 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, #define KSEG2_BASE 0xC0000000UL #define KSEG3_BASE 0xE0000000UL +#define KVM_KSEG0_BASE 0x40000000UL +#define KVM_KSEG2_BASE 0x60000000UL + + if (kvm_enabled()) { + /* KVM T&E adds guest kernel segments in useg */ + if (real_address >= KVM_KSEG0_BASE) { + if (real_address < KVM_KSEG2_BASE) { + /* kseg0 */ + address += KSEG0_BASE - KVM_KSEG0_BASE; + } else if (real_address <= USEG_LIMIT) { + /* kseg2/3 */ + address += KSEG2_BASE - KVM_KSEG2_BASE; + } + } + } + if (address <= USEG_LIMIT) { /* useg */ if (env->CP0_Status & (1 << CP0St_ERL)) { *physical = address & 0xFFFFFFFF; *prot = PAGE_READ | PAGE_WRITE; } else { - ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); } #if defined(TARGET_MIPS64) } else if (address < 0x4000000000000000ULL) { /* xuseg */ if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } @@ -144,7 +163,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, /* xsseg */ if ((supervisor_mode || kernel_mode) && SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } @@ -161,7 +180,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, /* xkseg */ if (kernel_mode && KX && address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } @@ -185,7 +204,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, } else if (address < (int32_t)KSEG3_BASE) { /* sseg (kseg2) */ if (supervisor_mode || kernel_mode) { - ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } @@ -193,7 +212,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, /* kseg3 */ /* XXX: debug segment is not emulated */ if (kernel_mode) { - ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); + ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); } else { ret = TLBRET_BADADDR; } -- cgit v1.2.1 From e2132e0bba7751be7af7e3ebcd6f39e77f76d05e Mon Sep 17 00:00:00 2001 From: Sanjay Lal Date: Tue, 17 Jun 2014 23:10:32 +0100 Subject: target-mips: kvm: Add main KVM support for MIPS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement the main KVM arch API for MIPS. Signed-off-by: Sanjay Lal Signed-off-by: James Hogan Cc: Aurelien Jarno Cc: Gleb Natapov Cc: Paolo Bonzini Cc: Andreas Färber Cc: Peter Maydell Signed-off-by: Paolo Bonzini --- target-mips/kvm.c | 683 +++++++++++++++++++++++++++++++++++++++++++++++++ target-mips/kvm_mips.h | 26 ++ 2 files changed, 709 insertions(+) create mode 100644 target-mips/kvm.c create mode 100644 target-mips/kvm_mips.h (limited to 'target-mips') diff --git a/target-mips/kvm.c b/target-mips/kvm.c new file mode 100644 index 0000000000..844e5bbe5f --- /dev/null +++ b/target-mips/kvm.c @@ -0,0 +1,683 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * KVM/MIPS: MIPS specific KVM APIs + * + * Copyright (C) 2012-2014 Imagination Technologies Ltd. + * Authors: Sanjay Lal +*/ + +#include +#include +#include + +#include + +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" +#include "sysemu/kvm.h" +#include "cpu.h" +#include "sysemu/cpus.h" +#include "kvm_mips.h" + +#define DEBUG_KVM 0 + +#define DPRINTF(fmt, ...) \ + do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0) + +const KVMCapabilityInfo kvm_arch_required_capabilities[] = { + KVM_CAP_LAST_INFO +}; + +static void kvm_mips_update_state(void *opaque, int running, RunState state); + +unsigned long kvm_arch_vcpu_id(CPUState *cs) +{ + return cs->cpu_index; +} + +int kvm_arch_init(KVMState *s) +{ + /* MIPS has 128 signals */ + kvm_set_sigmask_len(s, 16); + + DPRINTF("%s\n", __func__); + return 0; +} + +int kvm_arch_init_vcpu(CPUState *cs) +{ + int ret = 0; + + qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); + + DPRINTF("%s\n", __func__); + return ret; +} + +void kvm_mips_reset_vcpu(MIPSCPU *cpu) +{ + DPRINTF("%s\n", __func__); +} + +int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) +{ + DPRINTF("%s\n", __func__); + return 0; +} + +int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) +{ + DPRINTF("%s\n", __func__); + return 0; +} + +static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) +{ + CPUMIPSState *env = &cpu->env; + + DPRINTF("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP))); + return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP)); +} + + +void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + int r; + struct kvm_mips_interrupt intr; + + if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_mips_io_interrupts_pending(cpu)) { + intr.cpu = -1; + intr.irq = 2; + r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); + if (r < 0) { + error_report("%s: cpu %d: failed to inject IRQ %x", + __func__, cs->cpu_index, intr.irq); + } + } +} + +void kvm_arch_post_run(CPUState *cs, struct kvm_run *run) +{ + DPRINTF("%s\n", __func__); +} + +int kvm_arch_process_async_events(CPUState *cs) +{ + return cs->halted; +} + +int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) +{ + int ret; + + DPRINTF("%s\n", __func__); + switch (run->exit_reason) { + default: + error_report("%s: unknown exit reason %d", + __func__, run->exit_reason); + ret = -1; + break; + } + + return ret; +} + +bool kvm_arch_stop_on_emulation_error(CPUState *cs) +{ + DPRINTF("%s\n", __func__); + return true; +} + +int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr) +{ + DPRINTF("%s\n", __func__); + return 1; +} + +int kvm_arch_on_sigbus(int code, void *addr) +{ + DPRINTF("%s\n", __func__); + return 1; +} + +void kvm_arch_init_irq_routing(KVMState *s) +{ +} + +int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) +{ + CPUState *cs = CPU(cpu); + struct kvm_mips_interrupt intr; + + if (!kvm_enabled()) { + return 0; + } + + intr.cpu = -1; + + if (level) { + intr.irq = irq; + } else { + intr.irq = -irq; + } + + kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); + + return 0; +} + +int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) +{ + CPUState *cs = current_cpu; + CPUState *dest_cs = CPU(cpu); + struct kvm_mips_interrupt intr; + + if (!kvm_enabled()) { + return 0; + } + + intr.cpu = dest_cs->cpu_index; + + if (level) { + intr.irq = irq; + } else { + intr.irq = -irq; + } + + DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq); + + kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); + + return 0; +} + +#define MIPS_CP0_32(_R, _S) \ + (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S))) + +#define MIPS_CP0_64(_R, _S) \ + (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S))) + +#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) +#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) +#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) +#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) +#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) +#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) +#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) +#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) +#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) +#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) +#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) +#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) +#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) +#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) + +/* CP0_Count control */ +#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ + 0x20000 | 0) +#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 /* master disable */ +/* CP0_Count resume monotonic nanoseconds */ +#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ + 0x20000 | 1) +/* CP0_Count rate in Hz */ +#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \ + 0x20000 | 2) + +static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, + int32_t *addr) +{ + uint64_t val64 = *addr; + struct kvm_one_reg cp0reg = { + .id = reg_id, + .addr = (uintptr_t)&val64 + }; + + return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); +} + +static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id, + target_ulong *addr) +{ + uint64_t val64 = *addr; + struct kvm_one_reg cp0reg = { + .id = reg_id, + .addr = (uintptr_t)&val64 + }; + + return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); +} + +static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id, + uint64_t *addr) +{ + struct kvm_one_reg cp0reg = { + .id = reg_id, + .addr = (uintptr_t)addr + }; + + return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg); +} + +static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id, + int32_t *addr) +{ + int ret; + uint64_t val64 = 0; + struct kvm_one_reg cp0reg = { + .id = reg_id, + .addr = (uintptr_t)&val64 + }; + + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); + if (ret >= 0) { + *addr = val64; + } + return ret; +} + +static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64 reg_id, + target_ulong *addr) +{ + int ret; + uint64_t val64 = 0; + struct kvm_one_reg cp0reg = { + .id = reg_id, + .addr = (uintptr_t)&val64 + }; + + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); + if (ret >= 0) { + *addr = val64; + } + return ret; +} + +static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64 reg_id, + uint64_t *addr) +{ + struct kvm_one_reg cp0reg = { + .id = reg_id, + .addr = (uintptr_t)addr + }; + + return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg); +} + +/* + * We freeze the KVM timer when either the VM clock is stopped or the state is + * saved (the state is dirty). + */ + +/* + * Save the state of the KVM timer when VM clock is stopped or state is synced + * to QEMU. + */ +static int kvm_mips_save_count(CPUState *cs) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + uint64_t count_ctl; + int err, ret = 0; + + /* freeze KVM timer */ + err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); + if (err < 0) { + DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err); + ret = err; + } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { + count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; + err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); + if (err < 0) { + DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); + ret = err; + } + } + + /* read CP0_Cause */ + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err); + ret = err; + } + + /* read CP0_Count */ + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err); + ret = err; + } + + return ret; +} + +/* + * Restore the state of the KVM timer when VM clock is restarted or state is + * synced to KVM. + */ +static int kvm_mips_restore_count(CPUState *cs) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + uint64_t count_ctl; + int err_dc, err, ret = 0; + + /* check the timer is frozen */ + err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); + if (err_dc < 0) { + DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc); + ret = err_dc; + } else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) { + /* freeze timer (sets COUNT_RESUME for us) */ + count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC; + err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); + if (err < 0) { + DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err); + ret = err; + } + } + + /* load CP0_Cause */ + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err); + ret = err; + } + + /* load CP0_Count */ + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err); + ret = err; + } + + /* resume KVM timer */ + if (err_dc >= 0) { + count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC; + err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl); + if (err < 0) { + DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err); + ret = err; + } + } + + return ret; +} + +/* + * Handle the VM clock being started or stopped + */ +static void kvm_mips_update_state(void *opaque, int running, RunState state) +{ + CPUState *cs = opaque; + int ret; + uint64_t count_resume; + + /* + * If state is already dirty (synced to QEMU) then the KVM timer state is + * already saved and can be restored when it is synced back to KVM. + */ + if (!running) { + if (!cs->kvm_vcpu_dirty) { + ret = kvm_mips_save_count(cs); + if (ret < 0) { + fprintf(stderr, "Failed saving count\n"); + } + } + } else { + /* Set clock restore time to now */ + count_resume = get_clock(); + ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME, + &count_resume); + if (ret < 0) { + fprintf(stderr, "Failed setting COUNT_RESUME\n"); + return; + } + + if (!cs->kvm_vcpu_dirty) { + ret = kvm_mips_restore_count(cs); + if (ret < 0) { + fprintf(stderr, "Failed restoring count\n"); + } + } + } +} + +static int kvm_mips_put_cp0_registers(CPUState *cs, int level) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + int err, ret = 0; + + (void)level; + + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, + &env->CP0_Context); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, + &env->active_tc.CP0_UserLocal); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, + &env->CP0_PageMask); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, + &env->CP0_BadVAddr); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err); + ret = err; + } + + /* If VM clock stopped then state will be restored when it is restarted */ + if (runstate_is_running()) { + err = kvm_mips_restore_count(cs); + if (err < 0) { + ret = err; + } + } + + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, + &env->CP0_EntryHi); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, + &env->CP0_Compare); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, + &env->CP0_ErrorEPC); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); + ret = err; + } + + return ret; +} + +static int kvm_mips_get_cp0_registers(CPUState *cs) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + int err, ret = 0; + + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, + &env->CP0_Context); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL, + &env->active_tc.CP0_UserLocal); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK, + &env->CP0_PageMask); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR, + &env->CP0_BadVAddr); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI, + &env->CP0_EntryHi); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE, + &env->CP0_Compare); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err); + ret = err; + } + + /* If VM clock stopped then state was already saved when it was stopped */ + if (runstate_is_running()) { + err = kvm_mips_save_count(cs); + if (err < 0) { + ret = err; + } + } + + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, + &env->CP0_ErrorEPC); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); + ret = err; + } + + return ret; +} + +int kvm_arch_put_registers(CPUState *cs, int level) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + struct kvm_regs regs; + int ret; + int i; + + /* Set the registers based on QEMU's view of things */ + for (i = 0; i < 32; i++) { + regs.gpr[i] = env->active_tc.gpr[i]; + } + + regs.hi = env->active_tc.HI[0]; + regs.lo = env->active_tc.LO[0]; + regs.pc = env->active_tc.PC; + + ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); + + if (ret < 0) { + return ret; + } + + ret = kvm_mips_put_cp0_registers(cs, level); + if (ret < 0) { + return ret; + } + + return ret; +} + +int kvm_arch_get_registers(CPUState *cs) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + int ret = 0; + struct kvm_regs regs; + int i; + + /* Get the current register set as KVM seems it */ + ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); + + if (ret < 0) { + return ret; + } + + for (i = 0; i < 32; i++) { + env->active_tc.gpr[i] = regs.gpr[i]; + } + + env->active_tc.HI[0] = regs.hi; + env->active_tc.LO[0] = regs.lo; + env->active_tc.PC = regs.pc; + + kvm_mips_get_cp0_registers(cs); + + return ret; +} diff --git a/target-mips/kvm_mips.h b/target-mips/kvm_mips.h new file mode 100644 index 0000000000..54f59656ef --- /dev/null +++ b/target-mips/kvm_mips.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * KVM/MIPS: MIPS specific KVM APIs + * + * Copyright (C) 2012-2014 Imagination Technologies Ltd. + * Authors: Sanjay Lal +*/ + +#ifndef __KVM_MIPS_H__ +#define __KVM_MIPS_H__ + +/** + * kvm_mips_reset_vcpu: + * @cpu: MIPSCPU + * + * Called at reset time to set kernel registers to their initial values. + */ +void kvm_mips_reset_vcpu(MIPSCPU *cpu); + +int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level); +int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level); + +#endif /* __KVM_MIPS_H__ */ -- cgit v1.2.1 From 14c03ab97594d0700d73aedc254579a57b8aeec1 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 17 Jun 2014 23:10:33 +0100 Subject: target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset() When KVM is enabled call kvm_mips_reset_vcpu() from mips_cpu_reset() as done for other targets since commit 50a2c6e55fa2 (kvm: reset state from the CPU's reset method). Signed-off-by: James Hogan Cc: Aurelien Jarno Cc: Paolo Bonzini Cc: Gleb Natapov Signed-off-by: Paolo Bonzini --- target-mips/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target-mips') diff --git a/target-mips/cpu.c b/target-mips/cpu.c index dd954fc55a..b3e0e6cce7 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -19,7 +19,9 @@ */ #include "cpu.h" +#include "kvm_mips.h" #include "qemu-common.h" +#include "sysemu/kvm.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) @@ -87,6 +89,12 @@ static void mips_cpu_reset(CPUState *s) tlb_flush(s, 1); cpu_state_reset(env); + +#ifndef CONFIG_USER_ONLY + if (kvm_enabled()) { + kvm_mips_reset_vcpu(cpu); + } +#endif } static void mips_cpu_realizefn(DeviceState *dev, Error **errp) -- cgit v1.2.1 From 222e7d11e7c35de5d7e4125da9a8f8dc937b6438 Mon Sep 17 00:00:00 2001 From: Sanjay Lal Date: Tue, 17 Jun 2014 23:10:36 +0100 Subject: target-mips: Enable KVM support in build system Enable KVM support for MIPS in the build system. Signed-off-by: Sanjay Lal Signed-off-by: James Hogan Reviewed-by: Aurelien Jarno Signed-off-by: Paolo Bonzini --- target-mips/Makefile.objs | 1 + 1 file changed, 1 insertion(+) (limited to 'target-mips') diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs index 0277d56e82..716244f3d5 100644 --- a/target-mips/Makefile.objs +++ b/target-mips/Makefile.objs @@ -1,3 +1,4 @@ obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o obj-y += gdbstub.o obj-$(CONFIG_SOFTMMU) += machine.o +obj-$(CONFIG_KVM) += kvm.o -- cgit v1.2.1