From ae52bd96ceaea36c486d8ffeb798e160f31d3be8 Mon Sep 17 00:00:00 2001 From: Sebastian Macke Date: Tue, 22 Oct 2013 02:12:40 +0200 Subject: target-openrisc: Correct wrong epcr register in interrupt handler This patch corrects several misbehaviors during an interrupt process. Most of the time the pc is already correct and therefore no special treatment of the exceptions is necessary. Tested by checking crashing programs which otherwise work in or1ksim. Signed-off-by: Sebastian Macke Reviewed-by: Jia Liu Signed-off-by: Jia Liu --- target-openrisc/interrupt.c | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) (limited to 'target-openrisc') diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 16ef4b3e79..2153e7ea7e 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -30,26 +30,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs) OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; #ifndef CONFIG_USER_ONLY - if (env->flags & D_FLAG) { /* Delay Slot insn */ + + env->epcr = env->pc; + if (env->flags & D_FLAG) { env->flags &= ~D_FLAG; env->sr |= SR_DSX; - if (env->exception_index == EXCP_TICK || - env->exception_index == EXCP_INT || - env->exception_index == EXCP_SYSCALL || - env->exception_index == EXCP_FPE) { - env->epcr = env->jmp_pc; - } else { - env->epcr = env->pc - 4; - } - } else { - if (env->exception_index == EXCP_TICK || - env->exception_index == EXCP_INT || - env->exception_index == EXCP_SYSCALL || - env->exception_index == EXCP_FPE) { - env->epcr = env->npc; - } else { - env->epcr = env->pc; - } + env->epcr -= 4; + } + if (env->exception_index == EXCP_SYSCALL) { + env->epcr += 4; } /* For machine-state changed between user-mode and supervisor mode, -- cgit v1.2.1