From 2495152227b73a277019453990eac4025220156b Mon Sep 17 00:00:00 2001 From: aurel32 Date: Sat, 24 Jan 2009 15:08:00 +0000 Subject: target-ppc: Add float register read/write using XML Signed-off-by: Nathan Froyd Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'target-ppc') diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 5ef7154ca7..21cb894650 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9272,6 +9272,33 @@ static void dump_ppc_insns (CPUPPCState *env) } #endif +static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + stfq_p(mem_buf, env->fpr[n]); + return 8; + } + if (n == 32) { + /* FPSCR not implemented */ + memset(mem_buf, 0, 4); + return 4; + } + return 0; +} + +static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + env->fpr[n] = ldfq_p(mem_buf); + return 8; + } + if (n == 32) { + /* FPSCR not implemented */ + return 4; + } + return 0; +} + int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) { env->msr_mask = def->msr_mask; @@ -9284,6 +9311,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) if (create_ppc_opcodes(env, def) < 0) return -1; init_ppc_proc(env, def); + + if (def->insns_flags & PPC_FLOAT) { + gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg, + 33, "power-fpu.xml", 0); + } #if defined(PPC_DUMP_CPU) { const char *mmu_model, *excp_model, *bus_model; -- cgit v1.2.1